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596
CAMEO:A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
"... Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of main memory increases the effective capacity, but obtaining high performance from such a system requires Operating System (OS) support ..."
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Cited by 1 (0 self)
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Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of main memory increases the effective capacity, but obtaining high performance from such a system requires Operating System (OS) support
Hardware-managed register allocation for embedded processors
- in LCTES ’04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and
, 2004
"... Most modern processors (either embedded or general purpose) contain higher number of physical registers than those exposed in the ISA. Due to a variety of reasons, this phenomenon is likely to continue especially on embedded systems where encoding space is very limited. Saving the encoding space lea ..."
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Cited by 4 (1 self)
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at ISA level. In this paper, we therefore propose a hardware managed register allocation scheme to allocate more physical registers at runtime and to utilize them. As a byproduct, we also show that hardware managed register allocation has other merits such as better exploitation of low register pressure
Toward Cache-Friendly Hardware Accelerators
"... Increasing demand for power-efficient, high-performance computing has spurred a growing number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as servers and desktops. Despite their energy efficiency, fixed-function accelerators lack programmability, especially compar ..."
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limitations of scratchpad-based memo-ries in today’s accelerators, identifies challenges to support hardware-managed caches, and explores opportunities to ease the cache integration. 1.
Cache Design for Embedded Real-Time Systems
- Proceedings of the Embedded Systems Conference, Summer
, 1999
"... Caches have long been a mechanism for speeding memory access and are popular in embedded hardware architectures from microcontrollers to core-based ASIC designs. However, caches are considered ill-suited for embedded real-time systems because they provide a probabilistic performance boost— a cache m ..."
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Cited by 9 (0 self)
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organizations that provide the benefit of caching without the real-time drawbacks of hardware-managed caches. These are software-managed caches, and several different examples can be found, from DSP-style on-chip RAM to academic designs. This paper compares the operation and organization of caches as found
Instruction Cache Locking inside a Binary Rewriter ∗
"... Cache memories in embedded systems play an important role in reducing the execution time of the applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, thus improving the run-time over a purely hardware-managed cache. Novel ..."
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Cited by 3 (0 self)
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Cache memories in embedded systems play an important role in reducing the execution time of the applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, thus improving the run-time over a purely hardware-managed cache
Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems
, 2006
"... In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees v ..."
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Cited by 73 (4 self)
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In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
"... Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in performance, power and area cost, and has the added advantage of better time predictability. This paper introduces a general-pur ..."
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Cited by 32 (7 self)
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Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in performance, power and area cost, and has the added advantage of better time predictability. This paper introduces a general
A Survey of Techniques for Managing and . . .
- JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS
, 2014
"... Initially introduced as special-purpose accelerators for graphics applications, GPUs have now emerged as general purpose computing platforms for a wide range of applications. To address the requirements of these applications, modern GPUs include sizable hardware-managed caches. However, several fact ..."
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Initially introduced as special-purpose accelerators for graphics applications, GPUs have now emerged as general purpose computing platforms for a wide range of applications. To address the requirements of these applications, modern GPUs include sizable hardware-managed caches. However, several
HYBRID COHERENCE FOR SCALABLE MULTICORE ARCHITECTURES
, 2010
"... This dissertation describes a cache architecture and memory model for 1000-core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a hybrid memory model that incorporates features from both software-managed coherence schemes and hardware-manage ..."
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This dissertation describes a cache architecture and memory model for 1000-core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a hybrid memory model that incorporates features from both software-managed coherence schemes and hardware-managed
Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth
, 2010
"... Abstract—Architectures that aggressively exploit SIMD often have many datapaths execute in lockstep and use multithreading to hide latency. They can yield high throughput in terms of area- and energy-efficiency for many dataparallel applications. To balance productivity and performance, many recent ..."
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Cited by 2 (2 self)
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SIMD organizations incorporate implicit cache hierarchies. Exaples of such architectures include Intel’s MIC, AMD’s Fusion, and NVIDIA’s Fermi. However, unlike software-managed streaming memories used in conventional graphics processors (GPUs), hardware-managed caches are more disruptive to SIMD
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