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Hardware Support for Clock Synchronization in

by Distributed Systems Martin, Martin Horauer - in Supplement of the 2001 International Conference on Dependable Systems and Networks , 2001
"... This article presents a novel network interface hardware architecture, which enables clock synchronization in fault-tolerant distributed real-time systems with sub-srange accuracy. The proposed mechanism, which is applicable for any packet-oriented data network, inserts time information into data pa ..."
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packets at the interface between the physical layer transceiver and the network controller upon packet transmission and receipt respectively. Local time is supplied by a high-resolution rate-adjustable adder-based clock, which also contains hardware support easing intervalbased external clock

Hardware Support for Interval Arithmetic

by J. Wolff V. Gudenberg, Lehrstuhl Fur Informatik Ii , 1995
"... At present the directed roundings of the IEEE standard for floating-point arithmetic only build a modest, but necessary base for interval arithmetic. Even if these are implemented in hardware, execution times for interval operations are disproportionately long. In this paper we investigate further h ..."
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hardware support for interval arithmetic. We discuss the design of specific interval components but also try to design units which are or can be used for traditional floating-point or other advanced arithmetic. 1 Introduction If we count rounded arithmetic operations only, interval arithmetic is slower

20 Locks: Hardware Support

by unknown authors
"... To go beyond Peterson’s algorithm and to build a working lock, we will need some help from our old friend, the hardware. Over the years, a number of different hardware primitives have been added to the instruction sets of various computer architectures; while we won’t study how these instructions ar ..."
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to correctly build locks. And thus we arrive at the crux of the problem: THE CRUX: HARDWARE LOCK SUPPORT What hardware support is needed to build locks and provide mutual exclusion for critical sections? Given new hardware primitives, how can we use them to build locks that are efficient and meet our

Hardware support for efficient virtualization

by John Fisher-ogden , 2006
"... Virtual machines have been used since the 1960’s in creative ways. From multiplexing expensive mainframes to providing backwards compatibility for customers migrating to new hard-ware, virtualization has allowed users to maximize their usage of limited hardware resources. Despite virtual machines fa ..."
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virtual machine be-comes critical. In this paper, we survey current research to-wards this end, focusing on the hardware support which en-ables efficient virtualization. Both Intel and AMD have incor-porated explicit support for virtualization into their CPU de-signs. While this can simplify the design

Hardware support for interval arithmetic

by Reinhard Kirchner, Universität Kaiserslautern, D- Kaiserslautern, Ulrich W. Kulisch, Universität Karlsruhe, D- Karlsruhe - Reliable Computing , 2006
"... Summary: A hardware unit for interval arithmetic (including division by an interval that contains zero) is described in this paper. After a brief introduction an instruction set for interval arithmetic is defined which is attractive from the mathematical point of view. These instructions consist of ..."
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Summary: A hardware unit for interval arithmetic (including division by an interval that contains zero) is described in this paper. After a brief introduction an instruction set for interval arithmetic is defined which is attractive from the mathematical point of view. These instructions consist

Hardware-Supported Virtualization on ARM

by Prashant Varanasi , Gernot Heiser - In Proceedings of the 2nd Asia-Pacific Workshop on Systems , 2011
"... ABSTRACT ARM is the dominant processor architecture for mobile devices and many other high-end embedded systems. Late last year ARM announced architectural support for virtualization, which will allow execution of unmodified guest operating system binaries. We have designed and implemented what we ..."
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believe is the first hypervisor supporting pure virtualization using those hardware extensions and evaluated it on simulated hardware. We describe our approach and report our initial experience with the architecture.

The Accumulation Buffer: Hardware Support for High-Quality Rendering

by Paul Haeberli, Kurt Akeley , 1990
"... This paper describes a system architecture that supports realtime generation of complex images, efficient generation of extremely high-quality images, and a smooth trade-off between the two. Based on the paradigm of integration, the architecture extends a state-of-the-art rendering system with an ad ..."
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This paper describes a system architecture that supports realtime generation of complex images, efficient generation of extremely high-quality images, and a smooth trade-off between the two. Based on the paradigm of integration, the architecture extends a state-of-the-art rendering system

Hardware Support for Priority Inheritance

by Bilge E. S. Akgul , Vincent J. Mooney III, Henrik Thane, Pramote Kuacharoen - RTSS , 2003
"... Previous work has shown that a system-on-a-chip lock cache (SoCLC) reduces on-chip memory traffic, provides a fair and fast lock hand-off, simplifies software, increases the real-time predictability of the system and improves performance. In this research work, we extend the SoCLC mechanism with a p ..."
Abstract - Cited by 5 (2 self) - Add to MetaCart
priority inheritance support implemented in hardware. Priority inheritance provides a higher level of real-time guarantees for synchronizing application tasks. Experimental results indicate that our SoCLC hardware mechanism with priority inheritance achieves a 36% speedup in lock delay, 88% speedup in lock

Hardware Support for Active Networking

by Ros G. Fragkiadakis, Nikolaos G. Bartzoudis, David J. Parish, Mark S, Alexandros Fragkiadakis - In Proceedings of The 2003 International Multiconference in Computer Science & Engineering (SAM'03), Las Vegas , 2003
"... A new reconfigurable active router architecture is presented in this paper. It consists of a software part and a hardware part. The software part is a set of kernelspace and user-space modules running on linux-PC. An FPGA PCI-based board with a Virtex-1600E FPGA forms the hardware part. The integrat ..."
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A new reconfigurable active router architecture is presented in this paper. It consists of a software part and a hardware part. The software part is a set of kernelspace and user-space modules running on linux-PC. An FPGA PCI-based board with a Virtex-1600E FPGA forms the hardware part

Implementing Hardware-supported

by Virtualization In Okl On Arm, Prashant Varanasi
"... Virtualization is an already popular trend in the desktop and server markets, and is becoming increasingly important on mobile devices, where ARM is the leading architecture. This thesis presents the design and implementation of a hypervisor integrating ARM’s recently announced virtualization extens ..."
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till hardware or a timing-accurate simulator is released. Acknowledgements I would especially like to thank my supervisor, Gernot Heiser, for his support and feedback throughout this thesis, and for the opportunity to undertake such an interesting thesis. I would also like to thank the staff at Open
Results 1 - 10 of 12,307