packets at the interface between the physical layer transceiver and the network controller upon packet transmission and receipt respectively. Local time is supplied by a high-resolution rate-adjustable adder-based clock, which also contains hardware support easing intervalbased external clock

hardware support for interval arithmetic. We discuss the design of specific interval components but also try to design units which are or can be used for traditional floating-point or other advanced arithmetic. 1 Introduction If we count rounded arithmetic operations only, interval arithmetic is slower

to correctly build locks. And thus we arrive at the crux of the problem: THE CRUX: HARDWARE LOCK SUPPORT What hardware support is needed to build locks and provide mutual exclusion for critical sections? Given new hardware primitives, how can we use them to build locks that are efficient and meet our

virtual machine be-comes critical. In this paper, we survey current research to-wards this end, focusing on the hardware support which en-ables efficient virtualization. Both Intel and AMD have incor-porated explicit support for virtualization into their CPU de-signs. While this can simplify the design

Summary: A hardware unit for interval arithmetic (including division by an interval that contains zero) is described in this paper. After a brief introduction an instruction set for interval arithmetic is defined which is attractive from the mathematical point of view. These instructions consist

is the first hypervisor supporting pure virtu-alization using those hardware extensions and evaluated it on simulated hardware. We describe our approach and report our initial experience with the architecture. Categories and Subject Descriptors

This paper describes a system architecture that supports realtime generation of complex images, efficient generation of extremely high-quality images, and a smooth trade-off between the two. Based on the paradigm of integration, the architecture extends a state-of-the-art rendering system

priority inheritance support implemented in hardware. Priority inheritance provides a higher level of real-time guarantees for synchronizing application tasks. Experimental results indicate that our SoCLC hardware mechanism with priority inheritance achieves a 36% speedup in lock delay, 88% speedup in lock

A new reconfigurable active router architecture is presented in this paper. It consists of a software part and a hardware part. The software part is a set of kernelspace and user-space modules running on linux-PC. An FPGA PCI-based board with a Virtex-1600E FPGA forms the hardware part

till hardware or a timing-accurate simulator is released. Acknowledgements I would especially like to thank my supervisor, Gernot Heiser, for his support and feedback throughout this thesis, and for the opportunity to undertake such an interesting thesis. I would also like to thank the staff at Open