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Analysis of AES Hardware Implementations

by Song J. Park - PREPRINT , 2003
"... Following paper examines hardware implementation methods regarding Advanced Encryption Standard (AES). Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed. An overview of existing AES hardware implementation techniques are summariz ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
Following paper examines hardware implementation methods regarding Advanced Encryption Standard (AES). Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed. An overview of existing AES hardware implementation techniques

HARDWARE IMPLEMENTATION OF AES ALGORITHM

by Marko Mali, Franc Novak, Anton Biasizzo
"... The paper presents a hardware implementation of the AES algorithm developed for an external data storage unit in a dependable application. The algorithm was implemented in FPGA using the development board Celoxica RC1000 and development suite Celoxica DK. The purpose of this prototype version was to ..."
Abstract - Cited by 6 (1 self) - Add to MetaCart
The paper presents a hardware implementation of the AES algorithm developed for an external data storage unit in a dependable application. The algorithm was implemented in FPGA using the development board Celoxica RC1000 and development suite Celoxica DK. The purpose of this prototype version

Perspectives on dedicated hardware implementations.

by unknown authors
"... Abstract. Algorithms, applications and hardware implementations of neural networks are not investigated in close connection. Researchers working in the development of dedicated hardware implementations de-velop simplied versions of otherwise complex neural algorithms or de-velop dedicated algorithms ..."
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Abstract. Algorithms, applications and hardware implementations of neural networks are not investigated in close connection. Researchers working in the development of dedicated hardware implementations de-velop simplied versions of otherwise complex neural algorithms or de-velop dedicated

Hardware Implementation of Ciphers

by Hari Priya Machiraju
"... With the rapid growth in computer systems and electronic communications using virtual networks, the demand for a secure encryption has increased and with it the demand for high performance hardware implementations of the cryptographic algorithms. This paper studies the performances of different hard ..."
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With the rapid growth in computer systems and electronic communications using virtual networks, the demand for a secure encryption has increased and with it the demand for high performance hardware implementations of the cryptographic algorithms. This paper studies the performances of different

HARDWARE IMPLEMENTATION OF RANK CODEC

by Igor Sysoev, Ernst Gabidulin
"... The authors present a hardware implementation of the codec for rank codes. Parameters of rank code are (8,4,5). Algorithm was implemented on FPGA Spartan 3. Code rate is 1/2. The codec operates with elements from Galois field GF(2 8). The device can process informational data stream up to 77 MiB/s ..."
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The authors present a hardware implementation of the codec for rank codes. Parameters of rank code are (8,4,5). Algorithm was implemented on FPGA Spartan 3. Code rate is 1/2. The codec operates with elements from Galois field GF(2 8). The device can process informational data stream up to 77 Mi

Hardware Implementation Low Power

by High Speed, Fft Core, I Kannan, Srinivasa Srivatsa , 2007
"... Abstract: In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia computing and high-speed wired and wireless communications. In response to these advances, the search for novel implementations of arithmetic-intensive circuitry has intensified. For t ..."
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. For the portability requirement in telecommunication systems, there is a need for low power hardware implementation of fast fourier transforms algorithm. This paper proposes the hardware implementation of low power multiplier-less radix-4 single–path delay commutator pipelined fast fourier transform processor

FPGA Prototyping of Hardware Implementation

by Er. Manoj Arora, Er. R S Chauhan, Er. Lalit Bagga
"... Abstract- In 1959 J. E. Volder presents a new algorithm for the real time solution of the equations raised in navigation system. This algorithm was the best replacement of analog navigation system by the digital. CORDIC algorithm used for the fast calculation of elementary functions like multiplicat ..."
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, signal processing and a lot more. This review paper presents the prototype of hardware implementation of CORDIC algorithm using Spartan –II series FPGA, with constraint to area efficiency and throughput architecture.

A Hardware Implementation of Pure Esterel

by Gérard Berry - ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, INDIAN ACADEMY OF SCIENCES, SADHANA , 1991
"... Esterel is a synchronous concurrent programming language dedicated to reactive systems (controllers, protocols, man-machine interfaces, etc.). Esterel has an efficient standard software implementation based on well-defined mathematical semantics. We present a new hardware implementation of the pure ..."
Abstract - Cited by 72 (3 self) - Add to MetaCart
Esterel is a synchronous concurrent programming language dedicated to reactive systems (controllers, protocols, man-machine interfaces, etc.). Esterel has an efficient standard software implementation based on well-defined mathematical semantics. We present a new hardware implementation of the pure

Neural Network Adaptations to Hardware Implementations

by Perry Moerland, Emile Fiesler , 1997
"... In order to take advantage of the massive parallelism offered by artificial neural networks, hardware implementations are essential. However, most standard neural network models are not very suitable for implementation in hardware and adaptations are needed. In this section an overview is given of t ..."
Abstract - Cited by 19 (1 self) - Add to MetaCart
In order to take advantage of the massive parallelism offered by artificial neural networks, hardware implementations are essential. However, most standard neural network models are not very suitable for implementation in hardware and adaptations are needed. In this section an overview is given

Hardware implementation of Similarity Functions

by Michael Freeman, Michael Weeks, Jim Austin - IADIS International Conference on Applied Computing , 2005
"... A number of applications varying from music to document classification, require the similarity between a collection of objects to be calculated. To achieve this, features about these objects are extracted e.g. keywords, shapes, colours, frequency components etc, to produce an N-dimensional feature v ..."
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. This paper investigates the possibility of accelerating these distance measures by using FPGA based hardware IP cores and compares this to a software implementation based on a Sun Blade 2000 computer.
Results 1 - 10 of 25,974