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5,043
Interprocedural optimization for dynamic hardware configurations
- in Proceedings of SAMOS 05
, 2005
"... Abstract. Little research in compiler optimizations has been undertaken to eliminate or diminish the negative influence on performance of the huge reconfiguration latency of the available FPGA platforms. In this paper, we propose an interprocedural optimization that minimizes the number of executed ..."
Abstract
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Cited by 1 (1 self)
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hardware configuration instructions taking into account constraints such as the ”FPGA-area placement conflicts ” between the available hardware configurations. The proposed algorithm allows the anticipation of hardware configuration instructions up to the application’s main procedure. The presented results
Hardware configuration.................................................................................................................... 4
"... Example environment overview............................................................................................................. 4 ..."
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Example environment overview............................................................................................................. 4
Hardware Configuration.................................................................. 4
, 2010
"... ..."
Instruction scheduling for dynamic hardware configurations
- In Design Automation and Test in Europe
, 2005
"... Although the huge reconfiguration latency of the avail-able FPGA platforms is a well-known shortcoming of the current FCCMs, little research in instruction scheduling has been undertaken to eliminate or diminish its negative influence on performance. In this paper, we introduce an instruction schedu ..."
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Cited by 1 (0 self)
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scheduling algorithm that minimizes the num-ber of executed hardware reconfiguration instructions tak-ing into account the ”FPGA area placement conflicts ” be-tween the available configurations. The algorithm is based on compiler analyses and feedback-directed techniques and it can switch from hardware
Runtime Task Mapping Based on Hardware Configuration Reuse
"... Abstract—In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on hardware configuration reuse, which tries to avoid the reconfiguration overhead of few selected tasks, by reusing the hardware configurations alr ..."
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Cited by 1 (1 self)
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Abstract—In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on hardware configuration reuse, which tries to avoid the reconfiguration overhead of few selected tasks, by reusing the hardware configurations
An Analysis of Hardware Configurations for an Adaptive Weightless Neural Network
"... Abstract- This paper examines the potential offered by adaptive hardware configurations of a class of weightless neural architecture called the Enhanced Probabilistic Convergent Network targeted on a Virtex-II pro FPGA which is re configurable. The reconfiguration and adaptive capability of the Enha ..."
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Abstract- This paper examines the potential offered by adaptive hardware configurations of a class of weightless neural architecture called the Enhanced Probabilistic Convergent Network targeted on a Virtex-II pro FPGA which is re configurable. The reconfiguration and adaptive capability
NexentaVSA for View Hardware Configuration Reference ii
"... Notice: No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or stored in a database or retrieval system for any purpose, without the express written permission of Nexenta Systems (hereinafter referr ..."
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registered trademark of Nexenta Systems in the United States and other countries. All other trademarks, service marks, and company names in this document are properties of their respective owners. NexentaVSA for View Hardware Configuration Reference iii
Solving Boolean Satisfiability with Dynamic Hardware Configurations
- In International Workshop on Field-Programmable Logic and Applications (FPL
, 1998
"... . Boolean satisfiability (SAT) is a core computer science problem with many important commercial applications. An NP-complete problem, many different approaches for accelerating SAT either in hardware or software have been proposed. In particular, our prior work studied mechanisms for accelerating S ..."
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Cited by 11 (1 self)
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SAT using configurable hardware to implement formula-specific solver circuits. In spite of this progress, SAT solver runtimes still show room for further improvement. In this paper, we discuss further improvements to configurable-hardwarebased SAT solvers. We discuss how dynamic techniques can be used
Results 1 - 10
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