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HARDWARE COMPLEXITY OF MICROPROCESSOR DESIGN ACCORDING

by To Moore’s Law, Haissam El-aawar
"... The increasing of the number of transistors on a chip, which plays the main role in improvement in the performance and increasing the speed of a microprocessor, causes rapidly increasing of microprocessor design complexity. Based on Moore’s Law the number of transistors should be doubled every 24 mo ..."
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months. The doubling of transistor count affects increasing of microprocessor design complexity, power dissipation, and cost of design effort. This article presents a proposal to discuss the matter of scaling hardware complexity of a microprocessor design related to Moore’s Law. Based on the discussion a

Reducing the Hardware Complexity and Processing Time

by unknown authors , 2007
"... The successful of parallel interference cancellation (PIC) to reduce the multiple access interference in wireless CDMA communication systems has motivated the communication community to investigate the potential of PIC in the optical CDMA domain. However, the drawback of PIC in optical domain is the ..."
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is the increase in demand for hardware in each receiver. As a result, it requires more complex hardware, higher processing time and cost. The hardware complexity increases in the receiver side of Optical PIC (OPIC) when the number of transmitter (users) increases which may require the upgrade of the entire system

Complexity-effective superscalar processors

by Subbarao Palacharla, J. E. Smith, et al. - IN PROCEEDINGS OF THE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE , 1997
"... The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated for ..."
Abstract - Cited by 467 (5 self) - Add to MetaCart
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated

STATEMATE: A Working Environment for the Development of Complex Reactive Systems

by David Harel, Hagi Lachover, Amnon Naamad, Amir Pnueli, Michal Politi, Rivi Sherman, Aharon Shtull-trauring, Mark Trakhtenbrot - IEEE Transactions on Software Engineering , 1990
"... This paper provides an overview of the STATEMATE system, constructed over the past several years by the authors and their colleagues at Ad Cad Ltd., the R&D subsidiary of i-Logix, Inc. STATEMATE is a set of tools, with a heavy graphical orientation, in- tended for the specification, analysis, d ..."
Abstract - Cited by 485 (7 self) - Add to MetaCart
, design, and documentation of large and complex reactive systems, such as real-time embedded sys- tems, control and communication systems, and interactive software or hardware. It enables a user to prepare, analyze, and debug diagram- matic, yet precise, descriptions of the system under development from

Token flow control

by Amit Kumar, et al.
"... As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design with route ..."
Abstract - Cited by 635 (35 self) - Add to MetaCart
to destination, approaching the communication energy-delaythroughput of dedicated wires. Our detailed implementation analysis shows TFC to be highly scalable and realizable at an aggressive target clock cycle delay of 21FO4 for large networks while requiring low hardware complexity. Evaluations of TFC using both

On the minimal Hardware Complexity of Pseudorandom Function Generators

by Matthias Krause, Stefan Lucks , 2000
"... . A set F of Boolean functions is called a pseudorandom function generator (PRFG) if communicating with a randomly chosen secret function from F cannot be efficiently distinguished from communicating with a truly random function. We ask for the minimal hardware complexity of a PRFG. This question is ..."
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. A set F of Boolean functions is called a pseudorandom function generator (PRFG) if communicating with a randomly chosen secret function from F cannot be efficiently distinguished from communicating with a truly random function. We ask for the minimal hardware complexity of a PRFG. This question

The x-Kernel: An Architecture for Implementing Network Protocols

by Norman C. Hutchinson, Larry L. Peterson - IEEE Transactions on Software Engineering , 1991
"... This paper describes a new operating system kernel, called the x-kernel, that provides an explicit architecture for constructing and composing network protocols. Our experience implementing and evaluating several protocols in the x-kernel shows that this architecture is both general enough to acc ..."
Abstract - Cited by 662 (21 self) - Add to MetaCart
abstractions through which processes running on those processors exchange messages. Network software is extremely complex: it must hide the details of the underlying hardware, recover from transmission failures, ensure that messages are delivered to the application processes in the appropriate order

A Model of Saliency-based Visual Attention for Rapid Scene Analysis

by Laurent Itti, Christof Koch, Ernst Niebur , 1998
"... A visual attention system, inspired by the behavior and the neuronal architecture of the early primate visual system, is presented. Multiscale image features are combined into a single topographical saliency map. A dynamical neural network then selects attended locations in order of decreasing salie ..."
Abstract - Cited by 1748 (72 self) - Add to MetaCart
Primates have a remarkable ability to interpret complex scenes in real time, despite the limited speed of the neuronal hardware available for such tasks. Intermediate and higher visual processes appear to select a subset of the available sensory information before further processing [1], most likely

Multiscalar Processors

by Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar - In Proceedings of the 22nd Annual International Symposium on Computer Architecture , 1995
"... Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distribute ..."
Abstract - Cited by 589 (30 self) - Add to MetaCart
Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks

Bandera: Extracting Finite-state Models from Java Source Code

by James C. Corbett, Matthew B. Dwyer, John Hatcliff, Shawn Laubach, Corina S. Pasareanu, Hongjun Zheng - IN PROCEEDINGS OF THE 22ND INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING , 2000
"... Finite-state verification techniques, such as model checking, have shown promise as a cost-effective means for finding defects in hardware designs. To date, the application of these techniques to software has been hindered by several obstacles. Chief among these is the problem of constructing a fini ..."
Abstract - Cited by 654 (33 self) - Add to MetaCart
Finite-state verification techniques, such as model checking, have shown promise as a cost-effective means for finding defects in hardware designs. To date, the application of these techniques to software has been hindered by several obstacles. Chief among these is the problem of constructing a
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