Results 1 - 10 of 352

Energy-driven integrated hardware-software optimizations using SimplePower

by N. Vijaykrishnan, M. J. Irwin, H. S. Kim, W. Ye , 2000
"... With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, area, and accuracy/precision as a major design constraint. Thus, designers must be concerned with both optimizing and estimating the energy consumption of circuits, architectures, and so ..."
Abstract - Cited by 143 (21 self) - Add to MetaCart
, and software. Most of the research in energy optimization and/or estimation has focused on single components of the system and has not looked across the interacting spectrum of the hardware and software. The novelty of our new energy estimation framework, SimplePower, isthatitevaluates the energy considering

DAISY: Dynamic Compilation for 100% Architectural Compatibility

by Kemal Ebcioglu, Erik R. Altman , 1997
"... Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instructi ..."
Abstract - Cited by 206 (13 self) - Add to MetaCart
Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected

Architecting the Cloud: Prospects and Problems

by Philip Achimugu, Oluwatolani Oluwagbemi, Victor Popoola
"... Highly-available and scalable web hosting can be a complex and expensive venture. Traditional scalable web architectures have not only needed to implement complex solutions to ensure high levels of reliability, but have also required an accurate forecast of traffic to provide a good quality of servi ..."
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of service (QoS) to clients. Dense peak traffic periods and wild swings in traffic patterns result in low utilization rates of expensive hardware, yielding high operating costs to maintain idle hardware, as well as an inefficient use of capital for underutilized hardware. As a result, this paper discusses

Hardware-Software Co-design, Tools for Architecting Systems-On-AChip

by Rajesh K Gupta - Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC , 1997
"... Abstract| This paper examines the issues and progress in the design of highly integrated microelectronic systems. These microsystems rely on an array of diverse components such as processors, memory, network interfaces, graphics and DSP`cores.' In particular, we discuss problems in the combine ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
in the combined design of hardware and software for these systems. We present a decomposition of the co-design problem, and identify the needed technologies in specication modeling, synthesis and validation for e cient and error-free system designs. Co-design tools along with domain-speci c design methodologies

Hardware/Compiler Codevelopment for an Embedded Media

by Christoforos Kozyrakis, David Judd, Joseph Gebis, Samuel Williams, David Patterson, Katherine Yelick - PROCEEDINGS OF THE IEEE , 2001
"... Embedded and portable systems running multimedia applications create a new challenge for hardware architects. A microprocessor for such applications needs to be easy to program like a general-purpose processor and have the performance and power efficiency of a digital signal processor. This paper pr ..."
Abstract - Cited by 12 (2 self) - Add to MetaCart
Embedded and portable systems running multimedia applications create a new challenge for hardware architects. A microprocessor for such applications needs to be easy to program like a general-purpose processor and have the performance and power efficiency of a digital signal processor. This paper

ARCHITECTING SKYBRIDGE-CMOS

by Architecting Skybridge-cmos, Mingyu Li , 2015
"... Manufacturing Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons This Open Access Thesis is brought to you for free and open access by the Dissertations and Theses at ScholarWorks@UMass Amherst. It has been accepted for inclusion in Masters Theses May 2014- current by an autho ..."
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Manufacturing Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons This Open Access Thesis is brought to you for free and open access by the Dissertations and Theses at ScholarWorks@UMass Amherst. It has been accepted for inclusion in Masters Theses May 2014- current

Architecting Systems and Virtual Machines

by Daisy Alexis Duck
"... The compelling unication of systems and the partition table has analyzed Web services, and current trends suggest that the explo-ration of compilers will soon emerge. Af-ter years of compelling research into Scheme, we verify the construction of the transistor, which embodies the intuitive principle ..."
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principles of adaptive hardware and architecture. We de-scribe a novel application for the understand-ing of the producer-consumer problem, which we call HotNotus. Such a hypothesis might seem perverse but never con icts with the need to provide rasterization to cyberneti-cists. 1

The System Architect's Workbench

by D. E. Thomas, E. M. Dirkes, R. A. Walker, J. V. Rajan, J. A. Nestor, R. L. Blackburn , 1988
"... This paper presents an overview of The System Architect's Workbench, a behavioral synthesis system under development at Carnegie Mellon University. This system converts an abstract behavioral description of a piece of hardware into a set of register-transfer components and a control sequence ta ..."
Abstract - Cited by 18 (1 self) - Add to MetaCart
This paper presents an overview of The System Architect's Workbench, a behavioral synthesis system under development at Carnegie Mellon University. This system converts an abstract behavioral description of a piece of hardware into a set of register-transfer components and a control sequence

Caisson: A Hardware Description Language for Secure Information Flow

by Xun Li, Mohit Tiwari, Jason K. Oberg, Vineeth Kashyap, Frederic T. Chong, Timothy Sherwood, Ben Hardekopf - IN PROCEEDINGS OF PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION (PLDI 2011 , 2011
"... Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s root of trust. We incorporate insights and techniques from designing information-flow secure programming languages to provide a ..."
Abstract - Cited by 16 (6 self) - Add to MetaCart
allows for an expressive, provably-secure HDL that operates at a familiar level of abstraction to the target audience of the language, hardware architects. We have implemented a compiler for Caisson that translates designs into Verilog and then synthesizes the designs using existing tools. As an example

Managing Wire Delay in Large Chip-Multiprocessor Caches

by Bradford M. Beckmann, David A. Wood - IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE , 2004
"... In response to increasing (relative) wire delay, architects have proposed various technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block migration (e.g., D-NUCA and NuRapid) reduces average hit latency by migrating frequently used blocks towards the lower-latency bank ..."
Abstract - Cited by 157 (4 self) - Add to MetaCart
In response to increasing (relative) wire delay, architects have proposed various technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block migration (e.g., D-NUCA and NuRapid) reduces average hit latency by migrating frequently used blocks towards the lower
Results 1 - 10 of 352