The term graceful degradation describes the smooth change to a lower state of some system aspect as a response to the occurrence of an event that prohibits the manifestation of the fully fledged system behavior. Graceful degradation has appeared in a variety of domains, from image processing

A pipeline is a linear array of processors with an input node at one end and an output node at the other end. This paper presents k-gracefully-degradable graphs which, given any set of up to k faults, contain a pipeline that uses all the healthy processor nodes. Our constructions are designed

of graceful degradation of timing, in the framework of our GESTYLE gesture markup language.

objective is to achieve graceful degradation in the presence of exceptions of any kind.

Distributed programs must often display graceful degradation, reacting adaptively to changes in the environment. Under ideal circumstances, the program’s behavior satisfies a set of application-dependent constraints. In the presence of failures, timing anomalies, or synchronization conflicts

are only passive. In this paper, we provide the first treatment of MPC with graceful degradation of both security and corruptions. First of all, our protocols provide graceful degradation of security, i.e., different security guarantees depending on the actual number of corrupted parties: the more

Design of gracefully degrading systems, where functionality is gradually reduced in the face of faults, has traditionally been a very difficult and error-prone task. General approaches to graceful degradation are typically limited to re-implementation of the system for a number of pre

considers defects in cache memory and studies their impact on program performance using a fault degradable cache model. We first describe how defects at the circuit level in cache manifest themselves at the microarchitecture level. We then examine several strategies for masking faults, by disabling faulty

This paper presents a method for evaluating the perfonnability of repairable degradable systems based upon combining Generalized Stochastic Petri Nets and product-form queueing network models. The method takes into con-sideration the transient behavior during a change in the system structure

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC datapaths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a systematic perturbation of the original