### TABLE 1 Gate Operation Matrices

2007

Cited by 2

### TABLE 5. Quantum Gate Operations Operation Description Operands

### TABLE 7. Quantum Gate Operations Operation Description Operands

### Table 1: The inequalities that must hold among the energy coeffi- cients for successful gate operation.

2003

"... In PAGE 4: ...Table 1: The inequalities that must hold among the energy coeffi- cients for successful gate operation. For our example, the set of inequalities that must hold is given in Table1 . Here we relate a valid state to all possible invalid states.... In PAGE 4: ...6 must evaluate to a lower energy state than all possible in- valid state. These relations are given in the 16 inequalities listed in Table1 . These inequalities can be solved using a proposed al- gorithm similar to Gaussian elimination where a variable that ap- pears with opposite signs in two equations can be eliminated.... In PAGE 4: ... These inequalities can be solved using a proposed al- gorithm similar to Gaussian elimination where a variable that ap- pears with opposite signs in two equations can be eliminated. Ap- plying this procedure to the inequalities in Table1 the following... ..."

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### Table 2: Operations for gates in 3-valued parallel simulation

"... In PAGE 4: ... Table 1 shows coding that is used for representing 3 values. W1 W2 value 0 1 0 1 0 1 1 1 X 0 0 unused Table 1: Coding for 3-valued logic in parallel simulation Table2 presents the operations performed with words W1 and W2 which code the gate input values. Here, A1 represents the word W1 of the line corresponding to the first input of the logic gate, and B1 denotes the W1 value for the second gate input.... ..."

### Table 7: Gate Counts and Delays of Operations in Design II

2002

"... In PAGE 14: ... The number of gates used in the iterative core circuit is slightly (about 3%) less than in [20]. The detailed gate counts and delays for Design II components are listed in Table7 . The Appendix describes the detailed implementation of LT1 and LT2.... ..."

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### Table 6: Gate Counts and Delays of Operations in Design I

2002

Cited by 4

### Table 2. Operations for gates in 3-valued parallel simulation operation W1 W2

"... In PAGE 2: ... Similarly, A2 and B2 denote the second bits of V1 and V2 respectively. Table2 presents the operations performed in parallel simulation. W1 and W2 indicate the first and second bits of the operation result.... ..."

### Table 1: Gate count for operation dependent on the bit widths of inputs n and m.

"... In PAGE 2: ... Note that the gate count for an operational unit varies with the bit width of its input variables (n,m). Table1 lists the estimation of the gate count number for the operations and their dependency on the bit widths of the inputs. Hence, from the longest path analysis we obtain for every type of operation the required gate count GCop,i.... ..."