Tools
Sorted by:
Try your query at:
 |
 |
 |
 |
 |
 |
Results 11 - 20
of
12,313
Table 9: Speedup of the ILP benchmarks relative to single-tile Raw. 1.4x slower by cycles and 2x slower by time than the full P3. This suggests that in the event that the parallelism in these applications is too small to be exploited across Raw tiles, a simple two-way Raw compute processor might be sufficient to make the performance dif- ference easily be hidden by other aspects of the system.
2004
"... In PAGE 7: ...0 Table 8: Performance of sequential programs on Raw and on a P3. Table9 shows the speedups achieved by Rawcc as the number of tiles varies from two to 16. The speedups are compared to per- formance of a single Raw tile.... ..."
Cited by 26
Table 9: Speedup of the ILP benchmarks relative to single-tile Raw. 1.4x slower by cycles and 2x slower by time than the full P3. This suggests that in the event that the parallelism in these applications is too small to be exploited across Raw tiles, a simple two-way Raw compute processor might be sufficient to make the performance dif- ference easily be hidden by other aspects of the system.
2004
"... In PAGE 7: ...0 Table 8: Performance of sequential programs on Raw and on a P3. Table9 shows the speedups achieved by Rawcc as the number of tiles varies from two to 16. The speedups are compared to per- formance of a single Raw tile.... ..."
Cited by 26
Table 9: Speedup of the ILP benchmarks relative to single-tile Raw. 1.4x slower by cycles and 2x slower by time than the full P3. This suggests that in the event that the parallelism in these applications is too small to be exploited across Raw tiles, a simple two-way Raw compute processor might be sufficient to make the performance dif- ference easily be hidden by other aspects of the system.
2004
"... In PAGE 7: ...0 Table 8: Performance of sequential programs on Raw and on a P3. Table9 shows the speedups achieved by Rawcc as the number of tiles varies from two to 16. The speedups are compared to per- formance of a single Raw tile.... ..."
Cited by 26
Table 9: Speedup of the ILP benchmarks relative to single-tile Raw. 1.4x slower by cycles and 2x slower by time than the full P3. This suggests that in the event that the parallelism in these applications is too small to be exploited across Raw tiles, a simple two-way Raw compute processor might be sufficient to make the performance dif- ference easily be hidden by other aspects of the system.
"... In PAGE 7: ...0 Table 8: Performance of sequential programs on Raw and on a P3. Table9 shows the speedups achieved by Rawcc as the number of tiles varies from two to 16. The speedups are compared to per- formance of a single Raw tile.... ..."
Table 1: Taxonomy of knowledge types for VE presentations (per Munro et al 2002). IRVEs are relatively new and the effectiveness of various information and interaction designs are not yet known. Nonetheless, we believe giving users a unified interactive experience of some process or phenomenon can improve learning, performance, and the accuracy of their mental models. While IRVEs provide the potential for users to integrate heterogeneous information from diverse sources in one session, most IRVEs are simplistic consisting of worlds with animations and labels or linked applications in external windows. Few exploit the full design space to give users flexible control over their views and interactions, but promising work is emerging in academia and industry that deserves mention.
2004
"... In PAGE 2: ... 2.0 Related Work Munro et al [2002] outlined the cognitive processing issues in virtual environments by the type of information they convey ( Table1 ). In reviewing VE presentations and tutoring systems, the authors note that VEs are especially appropriate for: navigation and locomotion in complex environments, manipulation of complex objects ad devices in 3D space, learning abstract concepts with spatial characteristics, complex data analysis, and decision making.... ..."
Cited by 1
Table 4: Performance reduction for the investigated approaches. Finally, table 5 shows the size of the equivalent fault classes for the three components obtained for the BIST engine, Sequential patterns and Full Scan approach applying the number of patterns reported in table 2. That result have been obtained exploiting an in-home developed tool in C language: this tool is able to build and analyze the diagnostic matrix by collecting each fault syn- dromes obtained by using Synopsys Tetramax as a fault simulator.
Table 3: Performance/Cost Trade-Offs of Exploiting Dual Data-Memory Banks
"... In PAGE 8: ... We include full duplication in the comparison to demonstrate the sig- nificant cost savings of duplicating only those arrays that would result in a performance gain when used in conjunction with parti- tioning. Table3 shows the Performance Gain (PG) of each technique rel- ative to the unoptimized case. Interestingly, full duplication does not always improve performance as much as the other techniques do.... In PAGE 8: ... Consequently, the average per- formance gain due to full duplication is less than the averages for partial duplication and the Ideal case. Table3 also shows the Cost Increase (CI) of each technique, due to changes in storage requirements, relative to the case when no memory parallelism is exploited. Here, it is important to note that changes in storage requirements include the effects on both instruction and data memories.... In PAGE 8: ... This is because parallel memory accesses are packed into fewer instruc- tions. Finally, Table3 lists the Performance/Cost Ratio (PCR) of each technique. PCR is the ratio of the Performance Gain to the Cost 0 5 10 15 20 25 30 35 40 45 50 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 Performance Gain (%) DSP Applications CBPr Dup Ideal a1 = adpcm a2 = lpc a3 = spectral a4 = edge_detect a5 = compress a6 = histogram a7 = V32encode a8= G721MLencode a9 = G721MLdecode a10 = G721WFencode a11 = trellis... ..."
Table 3: Performance/Cost Trade-Offs of Exploiting Dual Data-Memory Banks
"... In PAGE 8: ... We include full duplication in the comparison to demonstrate the sig- nificant cost savings of duplicating only those arrays that would result in a performance gain when used in conjunction with parti- tioning. Table3 shows the Performance Gain (PG) of each technique rel- ative to the unoptimized case. Interestingly, full duplication does not always improve performance as much as the other techniques do.... In PAGE 8: ... Consequently, the average per- formance gain due to full duplication is less than the averages for partial duplication and the Ideal case. Table3 also shows the Cost Increase (CI) of each technique, due to changes in storage requirements, relative to the case when no memory parallelism is exploited. Here, it is important to note that changes in storage requirements include the effects on both instruction and data memories.... In PAGE 8: ... This is because parallel memory accesses are packed into fewer instruc- tions. Finally, Table3 lists the Performance/Cost Ratio (PCR) of each technique. PCR is the ratio of the Performance Gain to the Cost 0 5 10 15 20 25 30 35 40 45 50 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 Performance Gain (%) DSP Applications CB Pr Dup Ideal a1 = adpcm a2 = lpc a3 = spectral a4 = edge_detect a5 = compress a6 = histogram a7 = V32encode a8= G721MLencode a9 = G721MLdecode a10 = G721WFencode a11 = trellis... ..."
Table 3: Performance/Cost Trade-Offs of Exploiting Dual Data-Memory Banks
"... In PAGE 8: ... We include full duplication in the comparison to demonstrate the sig- nificant cost savings of duplicating only those arrays that would result in a performance gain when used in conjunction with parti- tioning. Table3 shows the Performance Gain (PG) of each technique rel- ative to the unoptimized case. Interestingly, full duplication does not always improve performance as much as the other techniques do.... In PAGE 8: ... Consequently, the average per- formance gain due to full duplication is less than the averages for partial duplication and the Ideal case. Table3 also shows the Cost Increase (CI) of each technique, due to changes in storage requirements, relative to the case when no memory parallelism is exploited. Here, it is important to note that changes in storage requirements include the effects on both instruction and data memories.... In PAGE 8: ... This is because parallel memory accesses are packed into fewer instruc- tions. Finally, Table3 lists the Performance/Cost Ratio (PCR) of each technique. PCR is the ratio of the Performance Gain to the Cost 0 5 10 15 20 25 30 35 40 45 50 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 Performance Gain (%) DSP Applications CB Pr Dup Ideal a1 = adpcm a2 = lpc a3 = spectral a4 = edge_detect a5 = compress a6 = histogram a7 = V32encode a8= G721MLencode a9 = G721MLdecode a10 = G721WFencode a11 = trellis... ..."
Table 2: Full Search Trails vs. Start and End Points
"... In PAGE 6: ... To investigate the useful- ness of exploiting full search trails, we compared NDCG scores obtained on the HumanRanking dataset with full browsing trails versus those obtained using either just the starting points (search result clicks), or just the end points of the trails (search destina- tions). Table2 summarizes the results of these experiments for the three methods, which again were trained on the entire available set of search trails. These results show that for all methods, using the full naviga- tional data contained in search trails leads to better performance: taking into account all sites visited by users provides more data to the models, yielding more accurate relevance predictions.... ..."
Results 11 - 20
of
12,313
