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R.: Estimation of Real-Time Software Code Size using COSMIC FSM
- In: Proc. of the IEEE Intl. Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2009
, 2009
"... All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately. ..."
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All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.
Evolutionary Algorithm Approach for Symbolic FSM Traversals
- IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM
"... Abstract--State space traversal algorithms for Finite State Machine (FSM) models of synchronous sequential circuitry are used extensively in various formal verification approaches such as Equivalence Checking (EC) and model checking. Symbolic Binary Decision Diagram (BDD) based approaches have allow ..."
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allowed many FSM models to be verified due to the compact representations they provide. However, there still remain circuits for which the traversal cannot be carried out due to the size of the Transition Relation (TR) BDD becoming too large. Pruning algorithms designed to reduce the size of a BDD while
Chapter 1 The Finite State-ness of FSM-Hume
"... Abstract Hume is a domain-specific programming language targeting resourcebounded computations, such as real-time embedded systems. It is novel in being based on generalised concurrent bounded automata, controlled by transitions characterised by pattern matching on inputs and recursive function gene ..."
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generation of outputs. FSM-Hume is a strict finite state subset of Hume, where symbols are constrained to fixed size types and transition functions are non-recursive. Here we discuss the design of FSM-Hume and show that it is indeed classically finite state. 1.1
FSM-based programmable memory BIST with macro command
- in Proc. IEEE International 36 R&I, 2008, No4 Workshop on Memory Technology, Design, and Testing (MTDT’05
, 2005
"... We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a “macro command”, to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of het ..."
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We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a “macro command”, to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety
Multi-level Logic Optimization of FSM Networks
"... Current approaches to compute and exploit the flexibility of a com-ponent in an FSM network are all at the symbolic level [23, 30, 33, 31]. Conventionally, exploitation of this flexibility relies on state minimizers for incompletely specified FSM’s (ISFSM’s) or pseudo non-deterministic FSM’s (PNDFSM ..."
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networks can be made efficient and effective. Finally, we give preliminary results on some artificially constructed FSM networks. Preliminary results indicate that our approach can be effective in reducing the size of a component of an FSM network. 1
Functional details visualization and classification in the COSMIC FSM framework
"... Given the relevance of software functional size measurement to the industry and in practice, improved ways to represent and handle the measurement details can provide significant advantages and make possible to discover new interpretation and exploitation possibilities over measurement results. This ..."
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Given the relevance of software functional size measurement to the industry and in practice, improved ways to represent and handle the measurement details can provide significant advantages and make possible to discover new interpretation and exploitation possibilities over measurement results
Modeling Resource Sharing using FSM-SADF
"... Abstract—This paper proposes a modeling approach to capture the mapping of an application on a platform. The approach is based on Scenario-Aware Dataflow (SADF) models. In contrast to the related work, we express the complete design-space in a single formal SADF model. This allows us to have a compa ..."
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of the application. The size of the model is independent of the number of executions of the application. Since we are able to capture all this behavior in a single SADF model we can use available dataflow analysis, such as worst-case and best-case throughput and deadlock-freedom checking. Furthermore, since
FSM GIANT SWAMP TARO SALINITY TOLERANCE EVALUATION
"... Abstract Giant swamp taro (Cyrtosperma chamissonis or C. merkusii Schott) is an important crop at atolls and mountainous islands in Micronesia. However, some dwellers abandon their taro patches damaged by recurrent wave surges and salt-water intrusion. We addressed this issue about threatened food ..."
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years. We collected forty three cultivars from Chuuk and Pohnpei states of the Federated States of Micronesia. After morphological characterization of their petioles, leaves and corms, we identified 15 different groups. We determined percentage survival, mean sucker number, monthly mean corm size
FSM Re-Engineering and Its Application in Low Power State Encoding
, 2005
"... We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then re-construct a functionally equivalent but topologically different FSM based on the opt ..."
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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then re-construct a functionally equivalent but topologically different FSM based
FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design
- ASP-DAC
"... Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significant power reductions are possible with techniques based on finite state machine (FSM) decomposition. A serious limitation of previousl ..."
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of previously proposed techniques is that they require the state transition graph (STG) of the FSM to be given or extracted from the circuit. Since the size of the STG can be exponential on the number of registers in the circuit, explicit techniques can only be applied to relatively small sequential circuits
Results 1 - 10
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