Results 1  10
of
243,722
Formal Verification
"... Formal verification (FV) involves the use of logical reasoning to establish properties of a computer program (or hardware element, protocol etc.) In the purest form of FV, rigorous logical deduction is used to prove with full mathematical rigor that the program satisfies a logical specification. Thi ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
Formal verification (FV) involves the use of logical reasoning to establish properties of a computer program (or hardware element, protocol etc.) In the purest form of FV, rigorous logical deduction is used to prove with full mathematical rigor that the program satisfies a logical specification
On Formal Verification of . . .
, 1993
"... this paper, we have used recently developed tools in theoretical distributed systems to develop a framework for verification of distributed mutual exclusion algorithms that can be applied for formal and rigorous verification of these algorithms. We have modeled the execution of mutual exclusion algo ..."
Abstract
 Add to MetaCart
this paper, we have used recently developed tools in theoretical distributed systems to develop a framework for verification of distributed mutual exclusion algorithms that can be applied for formal and rigorous verification of these algorithms. We have modeled the execution of mutual exclusion
Formal verification of a realistic compiler
 Communications of the ACM
"... This paper reports on the development and formal verification (proof of semantic preservation) of CompCert, a compiler from Clight (a large subset of the C programming language) to PowerPC assembly code, using the Coq proof assistant both for programming the compiler and for proving its correctness. ..."
Abstract

Cited by 173 (19 self)
 Add to MetaCart
This paper reports on the development and formal verification (proof of semantic preservation) of CompCert, a compiler from Clight (a large subset of the C programming language) to PowerPC assembly code, using the Coq proof assistant both for programming the compiler and for proving its correctness
seL4: Formal Verification of an OS Kernel
 ACM SYMPOSIUM ON OPERATING SYSTEMS PRINCIPLES
, 2009
"... Complete formal verification is the only known way to guarantee that a system is free of programming errors. We present our experience in performing the formal, machinechecked verification of the seL4 microkernel from an abstract specification down to its C implementation. We assume correctness of ..."
Abstract

Cited by 288 (45 self)
 Add to MetaCart
Complete formal verification is the only known way to guarantee that a system is free of programming errors. We present our experience in performing the formal, machinechecked verification of the seL4 microkernel from an abstract specification down to its C implementation. We assume correctness
Formal Verification of Reconfigurable Cores
 Proc. Symp. on FieldProgrammable Custom Computing Machines, IEEE Computer
, 1999
"... We show how a formal verification methodology can complement conventional verification for the development of FPGAbased cores. As FPGAs become larger, there is a greater reliance on shrinkwrapped intellectual property. In particular, customers expect rigorous verification of the cores that they pur ..."
Abstract

Cited by 8 (0 self)
 Add to MetaCart
We show how a formal verification methodology can complement conventional verification for the development of FPGAbased cores. As FPGAs become larger, there is a greater reliance on shrinkwrapped intellectual property. In particular, customers expect rigorous verification of the cores
Formal verification of hybrid systems
, 2011
"... In formal verification, a designer first constructs a model, with mathematically precise semantics, of the system under design, and performs extensive analysis with respect to correctness requirements. The appropriate mathematical model for embedded control systems is hybrid systems that combines th ..."
Abstract

Cited by 32 (0 self)
 Add to MetaCart
In formal verification, a designer first constructs a model, with mathematically precise semantics, of the system under design, and performs extensive analysis with respect to correctness requirements. The appropriate mathematical model for embedded control systems is hybrid systems that combines
FORMAL VERIFICATION OF INDUSTRIAL CONTROLLERS: WITH OR
, 2009
"... The use of a plant model on formal verification of industrial controllers makes the formal verification tasks more realistic, because any industrial system is always composed by a controller and a plant. Therefore, if the plant model is not used, there is a part of the system that is not considered. ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
The use of a plant model on formal verification of industrial controllers makes the formal verification tasks more realistic, because any industrial system is always composed by a controller and a plant. Therefore, if the plant model is not used, there is a part of the system that is not considered
Formal verification made easy
, 1997
"... Formal verification (Fv) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verificat ..."
Abstract

Cited by 5 (0 self)
 Add to MetaCart
Formal verification (Fv) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal
Model Abstraction for Formal Verification
, 1998
"... As the complexity of circuit designs grows, designers look toward formal verification to achieve better test coverage for validating complex designs. However, this approach is inherently computationally intensive, and hence, only small designs can be verified using this method. To achieve better per ..."
Abstract

Cited by 3 (1 self)
 Add to MetaCart
As the complexity of circuit designs grows, designers look toward formal verification to achieve better test coverage for validating complex designs. However, this approach is inherently computationally intensive, and hence, only small designs can be verified using this method. To achieve better
Results 1  10
of
243,722