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TABLE 3-5 Machine Check Errors

in unknown title
by unknown authors 2005

Table 3: Description of the IA-64 Machine-Check System State. Flag Description

in Increasing Relevance of . . . -- A Case for Recoverable Programming Models
by Dejan Milojicic , Alan Messer, James Shau, Guangrui Fu, Alberto Munoz 2000
"... In PAGE 4: ...Table3 ). Depending on the processor/platform implementation, a combina- tion of these flags will be signalled to the operating sys- tem by the processor firmware.... ..."
Cited by 18

Table 3: Description of the IA-64 Machine-Check System State. Flag Description

in Increasing Relevance of Memory Hardware Errors - A Case for Recoverable Programming Models
by Dejan Milojicic, Alan Messer, James Shau, Guangrui Fu, Alberto Munoz 2000
"... In PAGE 4: ...Table3 ). Depending on the processor/platform implementation, a combina- tion of these flags will be signalled to the operating sys- tem by the processor firmware.... ..."
Cited by 18

TABLE 3-5 Machine Check Errors (Continued)

in unknown title
by unknown authors 2005

TABLE 2. Results of Formal Verification

in Establishing PCI Compliance using Formal Verification: a Case Study
by Ilan Beer, Shoham Ben-david, Cindy Eisner, Yechiel Engel, Raanan Gewirtzman, Avner L 1995
Cited by 4

Table 3: Accuracy of signatures in formal verification

in Library Based Technology Mapping Using Multiple Domain Representations
by J. Bullmann, E. Schubert, U. Kebschull, W. Rosenstiel, Forschungszentrum Informatik (fzi
"... In PAGE 4: ... Here, signatures are used to find variable corre- spondences in pairs of Boolean functions prior to formal verifica- tion. The results are shown in Table3 . Even for large functions with many inputs few variable order aliases are observed.... ..."

Table 1. Formal verification using BAN logic.

in (PerCom’04) PrudentExposure: A Private and User-centric Service Discovery Protocol
by Feng Zhu, Matt Mutka, Lionel Ni
"... In PAGE 9: ... The deduction is quite lengthy and we omit it. We only show the idealized protocol and stepwise results in Table1 and omit the detailed discussion of the process. Step 1 is trivial.... In PAGE 9: ... Since that member has the control over the generation of the Bloom filter, P believes the Bloom filter (Postulate (3)). Based on these postulates, we can mechanically deduct and get the results as shown in Table1 . Moreover, the logic forces us to explicitly write down our assumptions to clarify our design goals.... ..."

Table 2. University Formal Verification tools.

in unknown title
by unknown authors

Table 6: Summary of human effort for the verification in MDGs and FormalCheck

in On the Modeling and Verification of a Telecom System Block Using MDGs
by M. Hasan Zobair, Sofiène Tahar
"... In PAGE 28: ... On the other hand in FormalCheck, property checking on the implementation took about two man-weeks. Table6 gives a summary of human time taken to model and verify the design using both MDG and FormalCheck tools, where * means that FormalCheck does not need that modeling or verification phase. References [1] Bell Communication Research (BellCORE), SONET Transport Systems: Common Generic Criteria, GR-253-CORE, issue 2, December 1995.... ..."

Table 1. Results from formal verification of safety with the necessary invariant constraints.

in Using automatic case splits and efficient CNF translation to guide a SAT solver when formally verifying out-of-order processors
by Miroslav N. Velev
"... In PAGE 8: ... Safety was checked with the commutative correctness diagram used in [20][93][94][98]. Table1 shows the results from formal verification with the necessary invariant constraints. The old translation to CNF is without preserving the ITE-tree structure of equation arguments when eliminating equations, but using a disjunction of conjunctions.... ..."
Cited by 1
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