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Table 2. Results in the presence of a symmetric faulty node.

in unknown title
by unknown authors 2007
"... In PAGE 27: ... The faulty node still behaves randomly, but its effect at the receiving nodes is identical. As shown in Table2 , the maximum available memory is used to model check this case. Due to the BDD construction, the memory usage is far more than the Byzantine faulty case.... ..."

Table 1. Results in the presence of a Byzantine faulty node.

in unknown title
by unknown authors 2007
"... In PAGE 26: ... Table1 lists the results of model checking of the basic case for the stated propositions 1 through 5, where the duration of the Maintain and Restore states, PM and PT, are chosen to be PM = PT = Period = 10 and the maximum convergence time, Convergence_Time, is 30. As shown in Table 1, the maximum memory usage is about 2GB after applying the state space reduction techniques.... In PAGE 26: ...Table 1 lists the results of model checking of the basic case for the stated propositions 1 through 5, where the duration of the Maintain and Restore states, PM and PT, are chosen to be PM = PT = Period = 10 and the maximum convergence time, Convergence_Time, is 30. As shown in Table1 , the maximum memory usage is about 2GB after applying the state space reduction techniques. The amount of memory used and processing time needed depend on the BDD construction and the nature of the query.... ..."

Table 3. Results in the presence of a symmetric faulty node.

in unknown title
by unknown authors 2007

Table 4. Results in the presence of a symmetric faulty node.

in unknown title
by unknown authors 2007

Table 5. Results in the presence of a symmetric faulty node.

in unknown title
by unknown authors 2007

Table 1.5: Composed model replicate node de#0Cnitions for project faulty proc.

in UltraSAN - User's Manual, Version 3.0
by William H. Sanders, High-performance Computing

Table 1.6: Composed model join node de#0Cnitions for project faulty proc.

in UltraSAN - User's Manual, Version 3.0
by William H. Sanders, High-performance Computing

Table 1: Routing example from node 426513 in S6 in the presence of six faulty links

in unknown title
by unknown authors 1993
"... In PAGE 4: ... It represents the code executed by node u when receiving (m; d; f=w; visited; linklist) from node v. Table1 shows an example of routing from node 426513 in S6 in the presence of six faults, where some faults forced backtracking, others did not add any extra hops. 3.... ..."
Cited by 18

Table 1: Routing example from node 426513 in S6 in the presence of six faulty links

in unknown title
by unknown authors
"... In PAGE 4: ... It represents the code executed by node u when receiving (m; d; f=w; visited; linklist) from node v. Table1 shows an example of routing from node 426513 in S6 in the presence of six faults, where some faults forced backtracking, others did not add any extra hops. 3.... ..."

Table 3: Verification of some faulty implementations Experiment rean (sec.) counter-example (sec.) #nodes Memory (MB)

in Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration
by Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
"... In PAGE 12: ... The non- equivalence of each erroneous implementation with respect to the specification was detected automatically during the reachability analysis, and counter-examples were generated to help diagnose the errors. Table3 shows the results for these three experiments including separate CPU time columns for performing the reachability analysis and for generating the counter-example, Table 1: Size and generation time of some MDGs MDG #nodes #paths CPU time (sec.) q0 71 256 1 q7 8321 1675264 80 v7 8572 1677824 5 q8 11665 128128 150 v8 20225 1805952 10 q9 25985 256256 300 v9 46160 2062208 10 q10 4995 60360 1100 v10 51106 2122568 60 q11 1 1 60 Table 2: Experimental results on behavioral verification Equivalence verification CPU time (sec.... ..."
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