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Table 2. Effect of Code Placement on the Program Schedule.

in Code Positioning for VLIW Architectures
by Andrea Cilio And, Henk Corporaal
"... In PAGE 9: ...lot. Unoccupied transport slots contain a no-transport code. 4.2 Experimental Results Table2 summarizes the effect of code positioning on the program schedule. The cy- cle counts do not include the stall cycles due to instruction cache miss.... ..."

Table 1: Placement results

in ABSTRACT Block Placement with Symmetry Constraints based on the O-tree Non-Slicing Representation
by Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-kuan Cheng
"... In PAGE 4: ...The placement algorithm described in this paper has been imple- mented in C on a SUN ULTRA-60 workstation. Table1 displays the placement results obtained from several test cases. SP denotes symmetry pairs, SS denotes self-symmetric cells.... ..."

Table 2: The impact of free cells on physical synthesis for industrial designs with low utilization. We report the worst slack and total negative slack (TNS) after physical synthesis. During the placement stage of physical synthesis, we add free cells so that the whitespace available to the placer was reduced to 40%. Free cells are removed after global placement. All designs are routable after physical synthesis.

in On Whitespace and Stability in Physical Synthesis
by Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
"... In PAGE 8: ... Compacting a placement without physical synthesis in mind will severely limit the efficacy of the physical synthesis tools. We study the effect of free cells on physical synthesis in Table2 . We conduct our experiments on proprietary industrial benchmarks with varying row-utilization.... In PAGE 8: ... Free cells are removed after global placement. As seen from the results in Table2 , the worst slack and total negative slack for all the designs improve considerably by adding free cells during the global placement stage of physical synthesis. All the designs are routable even after compacting the designs by using free cells.... ..."

Table 2: The impact of free cells on physical synthesis for industrial designs with low utilization. We report the worst slack and total negative slack (TNS) after physical synthesis. During the placement stage of physical synthesis, we add free cells so that the whitespace available to the placer was reduced to 40%. Free cells are removed after global placement. All designs are routable after physical synthesis.

in On Whitespace and Stability in Physical Synthesis
by Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
"... In PAGE 8: ... Compacting a placement without physical synthesis in mind will severely limit the efficacy of the physical synthesis tools. We study the effect of free cells on physical synthesis in Table2 . We conduct our experiments on proprietary industrial benchmarks with varying row-utilization.... In PAGE 8: ... Free cells are removed after global placement. As seen from the results in Table2 , the worst slack and total negative slack for all the designs improve considerably by adding free cells during the global placement stage of physical synthesis. All the designs are routable even after compacting the designs by using free cells.... ..."

Table 5: Test cases for Standard-Cell Placement experiment.

in Effective Iterative Techniques for Fingerprinting Design IP
by Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong 1999
"... In PAGE 5: ... 5.4 Standard-Cell Placement For standard-cell placement, we have applied our fingerprinting technique to the four industry designs listed in Table5 . For each test case, we generate an initial solution S0 and a sequence of 20 different fingerprinted solutions S1;:::;S20; for each fingerprinted solution, the previous fingerprinted solution is used as the initial... ..."
Cited by 14

Table 2: Imagine placement results

in VLSI Design and Verification of the Imagine Processor
by Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles 2002
"... In PAGE 4: ... 5. Imagine Implementation Results Table2 shows the placement results for the subchips and top level design. Standard cell occupancy is given as a ratio of standard cell area to placeable area.... ..."
Cited by 1

Table 5: Test cases for Standard-Cell Placement experiment.

in Effective Iterative Techniques for Fingerprinting Design IP
by Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
"... In PAGE 5: ... 5.4 Standard-Cell Placement For standard-cell placement, we have applied our fingerprinting technique to the four industry designs listed in Table5 . For each test case, we generate an initial solution S0 and a sequence of 20 different fingerprinted solutions S1;:::;S20; for each fingerprinted solution, the previous fingerprinted solution is used as the initial... ..."

Table 5: Test cases for Standard-Cell Placement experiment.

in Effective Iterative Techniques for Fingerprinting Design IP
by Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
"... In PAGE 5: ... 5.4 Standard-Cell Placement For standard-cell placement, we have applied our fingerprinting technique to the four industry designs listed in Table5 . For each test case, we generate an initial solution S0 and a sequence of 20 different fingerprinted solutions S1;:::;S20; for each fingerprinted solution, the previous fingerprinted solution is used as the initial... ..."

Table 1. Test cell placement for parameter set I

in Hardware-Optimal Test Register Insertion
by Albrecht P. Stroele, Associate Member, Hans-joachim Wunderlich 1998
"... In PAGE 14: ...Stroele / Wunderlich For the validation of the algorithm, we are interested in provably optimal solutions, computing times, and the impact of the factor quality on the costs of the found solutions. The solutions and computing times on a SUN Sparc 10 workstation are listed in Table1 for parameter set I, and in Table 2 for parameter set II. The first column denotes the circuit, and #B, #Bt, #C, and #Ct are the number of BILBO cells, transparent BILBO cells, CBILBO cells, and transparent CBILBO cells, respectively.... ..."
Cited by 8

Table 2. Test cell placement for parameter set II

in Hardware-Optimal Test Register Insertion
by Albrecht P. Stroele, Associate Member, Hans-joachim Wunderlich 1998
"... In PAGE 14: ...Stroele / Wunderlich For the validation of the algorithm, we are interested in provably optimal solutions, computing times, and the impact of the factor quality on the costs of the found solutions. The solutions and computing times on a SUN Sparc 10 workstation are listed in Table 1 for parameter set I, and in Table2 for parameter set II. The first column denotes the circuit, and #B, #Bt, #C, and #Ct are the number of BILBO cells, transparent BILBO cells, CBILBO cells, and transparent CBILBO cells, respectively.... ..."
Cited by 8
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