Abstract not found

Extended digit multiplication can be an effective benchmark for comparing contemporary CPUs to other architectures and devices. The Great Internet Mersenne Prime Search (GIMPS), a distributed computing effort to find large prime numbers, has produced highly optimized code for multiplying large

and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power

We describe a method for removing noise from digital images, based on a statistical model of the coefficients of an overcomplete multiscale oriented basis. Neighborhoods of coefficients at adjacent positions and scales are modeled as the product of two independent random variables: a Gaussian

multiplier. The results are compared with Cartesian Genetic Programming (CGP) with and without PR and show that ECGP improves evolvability and also that PR im-proves the performance of both techniques by up to eight times on the digital multiplier problems tested. 1

Abstract. Embedded Cartesian Genetic Programming (ECGP) is a form of Genetic Programming based on an acyclic directed graph representation. In this paper we investigate the use of ECGP together with a technique called Product Reduction (PR) to reduce the time required to evolve a digital multiplier

Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices.The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal

Implementation

An optical parallel quaternary signed digit (QSD) two-dimensional array multiplier based on digit-decomposition (DDP) representation and duplication-shifting-superimposing algorithm is proposed in this paper. The multiplication operation is done in three steps; one for partial products generation

This paper presents a novel high-speed Binary CSD (BCSD) multiplier which takes advantage of the benefits coming from the Canonic Signed Digit (CSD) number system, while overcoming the inherent overhead due to the CSD ternary representation. BCSD is a binary number system which allows representing