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152,843
Polynomial identity testing for depth 3 circuits
 in Proceedings of the twentyfirst Annual IEEE Conference on Computational Complexity (CCC
, 2006
"... Abstract — We study ΣΠΣ(k) circuits, i.e., depth three arithmetic circuits with top fanin k. We give the first deterministic polynomial time blackbox identity test for ΣΠΣ(k) circuits over the field Q of rational numbers, thus resolving a question posed by Klivans and Spielman (STOC 2001). Our main ..."
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Cited by 51 (11 self)
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Abstract — We study ΣΠΣ(k) circuits, i.e., depth three arithmetic circuits with top fanin k. We give the first deterministic polynomial time blackbox identity test for ΣΠΣ(k) circuits over the field Q of rational numbers, thus resolving a question posed by Klivans and Spielman (STOC 2001). Our main
A Depth 3 Circuit Lower Bound for the Parity Function *
"... We consider small depth boolean circuits with basis {AND, OR, NOT}. We obtain lower bounds for the parity function using a relatively simple method. We prove that for any depth 3 circuit with top fanin t, computing the nvariable parity function n−1 must have at least depth 4 circuits. t t2 wires. ..."
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We consider small depth boolean circuits with basis {AND, OR, NOT}. We obtain lower bounds for the parity function using a relatively simple method. We prove that for any depth 3 circuit with top fanin t, computing the nvariable parity function n−1 must have at least depth 4 circuits. t t2 wires
Upper and Lower Bounds for Some Depth3 Circuit Classes
 In Proc. 12th Ann. IEEE Conf. Comput. Complexity Theory
, 1997
"... We investigate the complexity of depth3 threshold circuits with majority gates at the output, possibly negated AND gates at level two, and MODm gates at level one. We show that the fanin of the AND gates can be reduced to O(log n) in the case where m is unbounded, and to a constant in the case whe ..."
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Cited by 11 (1 self)
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We investigate the complexity of depth3 threshold circuits with majority gates at the output, possibly negated AND gates at level two, and MODm gates at level one. We show that the fanin of the AND gates can be reduced to O(log n) in the case where m is unbounded, and to a constant in the case
Blackbox identity testing for bounded top fanin depth3 circuits: the field doesn’t matter
 In Proceedings of the 43rd annual ACM Symposium on Theory of Computing (STOC
, 2011
"... Abstract. Let C be a depth3 circuit with n variables, degree d and top fanin k (called ΣΠΣ(k, d, n) circuits) over base field F. It is a major open problem to design a deterministic polynomial time blackbox algorithm that tests if C is identically zero. Klivans & Spielman (STOC 2001) observed ..."
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Cited by 20 (7 self)
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Abstract. Let C be a depth3 circuit with n variables, degree d and top fanin k (called ΣΠΣ(k, d, n) circuits) over base field F. It is a major open problem to design a deterministic polynomial time blackbox algorithm that tests if C is identically zero. Klivans & Spielman (STOC 2001) observed
FROM SYLVESTERGALLAI CONFIGURATIONS TO RANK BOUNDS: IMPROVED BLACKBOX IDENTITY TEST FOR DEPTH3 CIRCUITS
"... Abstract. We study the problem of identity testing for depth3 circuits of top fanin k and degree d (called ΣΠΣ(k, d) identities). We give a new structure theorem for such identities. A direct application of our theorem improves the known deterministic d kO(k) time blackbox identity test over ratio ..."
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Cited by 27 (6 self)
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Abstract. We study the problem of identity testing for depth3 circuits of top fanin k and degree d (called ΣΠΣ(k, d) identities). We give a new structure theorem for such identities. A direct application of our theorem improves the known deterministic d kO(k) time blackbox identity test over
From SylvesterGallai Congurations to Rank Bounds: Improved Blackbox Identity Test for Depth3 Circuits
"... We study the problem of identity testing for depth3 circuits of top fanin k and degree d. We give a new structure theorem for such identities that improves the known deterministic dk O(k)time blackbox identity test over rationals (Kayal & Saraf, FOCS 2009) to one that takes dO(k 2)time. Our s ..."
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We study the problem of identity testing for depth3 circuits of top fanin k and degree d. We give a new structure theorem for such identities that improves the known deterministic dk O(k)time blackbox identity test over rationals (Kayal & Saraf, FOCS 2009) to one that takes dO(k 2)time. Our
Locally Decodable Codes with 2 queries and Polynomial Identity Testing for depth 3 circuits
 ELECTRONIC COLLOQUIUM ON COMPUTATIONAL COMPLEXITY, REPORT NO. 44 (2005)
, 2005
"... In this work we study two, seemingly unrelated, notions. Locally Decodable Codes (LDCs) are codes that allow the recovery of each message bit from a constant number of entries of the codeword. Polynomial Identity Testing (PIT) is one of the fundamental problems of algebraic complexity: we are given ..."
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Cited by 55 (14 self)
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show that if E: F n ↦ → F m is a linear LDC with 2 queries then m = exp(Ω(n)). Previously this was only known for fields of size << 2 n [GKST01]. 2. We show that from every depth 3 arithmetic circuit (ΣΠΣ circuit), C, with a bounded (constant) top fanin that computes the zero polynomial, one can
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
LowPower CMOS Digital Design
 JOURNAL OF SOLIDSTATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413
, 1992
"... Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use the ..."
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Cited by 570 (20 self)
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Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use
A Framework for Dynamic Graph Drawing
 CONGRESSUS NUMERANTIUM
, 1992
"... Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized as follows ..."
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Cited by 627 (44 self)
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Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized
Results 1  10
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152,843