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The BSD Packet Filter: A New Architecture for User-level Packet Capture
, 1992
"... Many versions of Unix provide facilities for user-level packet capture, making possible the use of general purpose workstations for network monitoring. Because network monitors run as user-level processes, packets must be copied across the kernel/user-space protection boundary. This copying can be m ..."
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Cited by 568 (2 self)
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be minimized by deploying a kernel agent called a packet filter, which discards unwanted packets as early as possible. The original Unix packet filter was designed around a stack-based filter evaluator that performs sub-optimally on current RISC CPUs. The BSD Packet Filter (BPF) uses a new, registerbased
ReVirt: Enabling Intrusion Analysis through Virtual-Machine Logging and Replay
- In Proceedings of the 2002 Symposium on Operating Systems Design and Implementation (OSDI
, 2002
"... Rights to individual papers remain with the author or the author's employer. Permission is granted for noncommercial reproduction of the work for educational or research purposes. This copyright notice must be included in the reproduced paper. USENIX acknowledges all trademarks herein. Current ..."
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Cited by 469 (26 self)
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Rights to individual papers remain with the author or the author's employer. Permission is granted for noncommercial reproduction of the work for educational or research purposes. This copyright notice must be included in the reproduced paper. USENIX acknowledges all trademarks herein. Current
RISC CPU
, 2002
"... ♦ SAR and slope analog-to-digital converter comparison ♦ MCU best practice coding techniques ♦ Tools and resources ♦ “Flashing the LED ” tool refresher ..."
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♦ SAR and slope analog-to-digital converter comparison ♦ MCU best practice coding techniques ♦ Tools and resources ♦ “Flashing the LED ” tool refresher
A survey of peer-to-peer content distribution technologies
- ACM Computing Surveys
, 2004
"... Distributed computer architectures labeled “peer-to-peer ” are designed for the sharing of computer resources (content, storage, CPU cycles) by direct exchange, rather than requiring the intermediation or support of a centralized server or authority. Peer-to-peer architectures are characterized by t ..."
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Cited by 378 (7 self)
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Distributed computer architectures labeled “peer-to-peer ” are designed for the sharing of computer resources (content, storage, CPU cycles) by direct exchange, rather than requiring the intermediation or support of a centralized server or authority. Peer-to-peer architectures are characterized
A New Efficient Algorithm for Computing Gröbner Bases (F4)
- IN: ISSAC ’02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON SYMBOLIC AND ALGEBRAIC COMPUTATION
, 2002
"... This paper introduces a new efficient algorithm for computing Gröbner bases. To avoid as much as possible intermediate computation, the algorithm computes successive truncated Gröbner bases and it replaces the classical polynomial reduction found in the Buchberger algorithm by the simultaneous reduc ..."
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Cited by 365 (57 self)
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reduction of several polynomials. This powerful reduction mechanism is achieved by means of a symbolic precomputation and by extensive use of sparse linear algebra methods. Current techniques in linear algebra used in Computer Algebra are reviewed together with other methods coming from the numerical field
External Memory Algorithms and Data Structures
, 1998
"... Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast internal memory and slower external memory (such as disks) can be a major performance bottleneck. In this paper, we surve ..."
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Cited by 349 (23 self)
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using the parallel disk model (PDM). The three machine-independent measures of performance in PDM are the number of I/O operations, the CPU time, and the amount of disk space. PDM allows for multiple disks (or disk arrays) and parallel CPUs, and it can be generalized to handle tertiary storage
A dynamic-SDRAM-modecontrol scheme for low-power systems with a 32-bit risc cpu
- In Proceeding of International Symposium on Low Power Electronics and Design
, 2001
"... We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An anal ..."
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Cited by 5 (0 self)
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We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM
Designing a RISC CPU in Reversible Logic
"... Abstract—Driven by its promising applications, reversible logic received significant attention. As a result, an impressive progress has been made in the development of synthesis approaches, implementation of sequential elements, and hardware description languages. In this paper, these recent achieve ..."
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achievements are employed in order to design a RISC CPU in reversible logic that can execute software programs written in an assembler language. The respective combinational and sequential components are designed using state-of-the-art design techniques. I.
Complexity-effective Enhancements to a RISC CPU Architecture
"... The M.CORE TM RISC architecture has been developed to address the growing need for long battery life among today's embedded applications [4]. In this paper, we present several architectural enhancements to the M.CORE M3 processor. Specifically, we discuss the burst mode memory enhancements, t ..."
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The M.CORE TM RISC architecture has been developed to address the growing need for long battery life among today's embedded applications [4]. In this paper, we present several architectural enhancements to the M.CORE M3 processor. Specifically, we discuss the burst mode memory enhancements
Optimization of Simple CPU Core for FPGA M. Be vá
"... Programmable logic arrays (FPGAs) containing CPU core and custom logic present a viable implementation platform for the current generation of embedded systems. This approach offers higher flexibility and lower cost comparing to traditional implementation of separate microcontroller and glue-logic. I ..."
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-logic. Important design decision is the choice of the right CPU core. Current market offers large number of CPU cores ranging from tiny 4-bit cores to 32-bit RISC CPUs. These cores are typically compatible with some commercially available microcontroller family. Various clones of the popular Intel 8051 micro
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