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16,476
Critical Path Delay and Net Delay Reduced
"... Abstract—In this paper, a technique for synthesizing binary tree structure of a non-regenerative logic circuit functionality is proposed, that achieves delay optimization by reducing the logic depth. It also helps in minimizing the resources needed to implement the logic tree structure with FPGA as ..."
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II (XC2S30-6PQ208) and Virtex II Pro (XC2VP2-7FG256) FPGA logic families show that there is an explicit maximum combinational path delay optimization by about 7.14%, on an average; reduction in maximum net delay by about 11.8 % and overall decrease in resource utilization by 44.07%, and mean savings
Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts ∗
"... It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy ..."
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Cited by 1 (0 self)
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It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths
Ultra-Fast Interconnect Driven Cell Cloning For Minimizing Critical Path Delay
"... In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say ..."
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In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say
3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs ∗
"... Abstract — 3D Integrated Circuits (ICs) have been recently proposed as a solution to the increasing wire delay concerns in scaled technologies. At the same time, technology scaling leads to increasing variability in manufacturing process parameters, making it imperative to quantify the impact of the ..."
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Cited by 6 (0 self)
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very differently under the impact of process variations as compared to equivalent 2D designs. In particular, for the same number of critical paths, we show that a 3D design is always less likely to meet a pre-defined frequency target compared to its 2D counterpart. Furthermore, as opposed to models
Routing in a Delay Tolerant Network
, 2004
"... We formulate the delay-tolerant networking routing problem, where messages are to be moved end-to-end across a connectivity graph that is time-varying but whose dynamics may be known in advance. The problem has the added constraints of finite buffers at each node and the general property that no con ..."
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Cited by 621 (8 self)
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We formulate the delay-tolerant networking routing problem, where messages are to be moved end-to-end across a connectivity graph that is time-varying but whose dynamics may be known in advance. The problem has the added constraints of finite buffers at each node and the general property
A Delay-Tolerant Network Architecture for Challenged Internets
, 2003
"... The highly successful architecture and protocols of today’s Internet may operate poorly in environments characterized by very long delay paths and frequent network partitions. These problems are exacerbated by end nodes with limited power or memory resources. Often deployed in mobile and extreme env ..."
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Cited by 953 (12 self)
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The highly successful architecture and protocols of today’s Internet may operate poorly in environments characterized by very long delay paths and frequent network partitions. These problems are exacerbated by end nodes with limited power or memory resources. Often deployed in mobile and extreme
Token flow control
"... As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design with route ..."
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Cited by 635 (35 self)
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As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design
The Performance of TCP/IP for Networks with High Bandwidth-Delay Products and Random Loss.
- IEEE/ACM Trans. Networking,
, 1997
"... Abstract-This paper examines the performance of TCP/IP, the Internet data transport protocol, over wide-area networks (WANs) in which data traffic could coexist with real-time traffic such as voice and video. Specifically, we attempt to develop a basic understanding, using analysis and simulation, ..."
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Cited by 465 (6 self)
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, of the properties of TCP/IP in a regime where: 1) the bandwidth-delay product of the network is high compared to the buffering in the network and 2) packets may incur random loss (e.g., due to transient congestion caused by fluctuations in real-time traffic, or wireless links in the path of the connection
Cilk: An Efficient Multithreaded Runtime System
, 1995
"... Cilk (pronounced “silk”) is a C-based runtime system for multithreaded parallel programming. In this paper, we document the efficiency of the Cilk work-stealing scheduler, both empirically and analytically. We show that on real and synthetic applications, the “work” and “critical path ” of a Cilk co ..."
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Cited by 763 (33 self)
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Cilk (pronounced “silk”) is a C-based runtime system for multithreaded parallel programming. In this paper, we document the efficiency of the Cilk work-stealing scheduler, both empirically and analytically. We show that on real and synthetic applications, the “work” and “critical path ” of a Cilk
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