"... In PAGE 9: ...9 From data in Table 4 we estimate the theoretically equivalent conventional cache capacity as explained in section 4.1, and show these results in Table5 . We have omitted the Jacobi values in estimating the average because they show very large values and unusual behavior.... ..."

"... In PAGE 11: ...ache is separated into a narrow bank and wide bank as explained in Section 2.3. In addition to accessing the wide bank in a direct-mapped fashion, the cache bitslicing technique is employed to save additional decode power. Table2 shows data comparison between our pipelined data cache and conventional data cache. The data shown is for 16KB, 4-way cache with 64B blocks.... In PAGE 12: ...he number of cycles needed to access the cache from two cycles to one. Section 4.3 explores the performance benefits from this reduction in cache access latency. Energy consumption is also shown in Table2 for both cache and store queue. Our cache con- sumes 0.... In PAGE 13: ...3, exploits the 0.6 ns exposed wide-cache latency from Table2 to reduce cache access to one cycle. 4 .... In PAGE 19: ... In this improved refetch replay configu- ration, referred as optimized scheme, we assume one cycle exposed cache access latency rather than two cycles latency. As shown in Table2 , this is a reasonable assumption. Our optimized Figure 12: SPEC INT (upper) and SPEC FP (lower) Number of pipeline flush recovery due to branch misprediction and load misscheduling.... ..."

"... In PAGE 12: ... More details on this approach are provided in [10]. Table4 shows data comparison between our pipelined data cache with bitslicing technique and a conven- tional data cache. The data shown is for 16KB, 4-way cache with 64B blocks.... In PAGE 13: ... However, since we already have the necessary bits to index the cache, the only operations needed after the full bits are available are tag comparison and output mux drive. In Table4 , this number, shown in parentheses, is only 0.6ns.... In PAGE 13: ...eeded to access the cache from two cycles into one cycle. Section 5.2 explores the performance benefits that derive from this reduction in cache access latency. Total energy consumption comparison is also shown in Table4 . Our cache consumes 0.... In PAGE 21: ... In this improved refetch replay config- uration, we assume one cycle cache access latency rather than two cycles latency. As shown in Table4 , this is a rea- sonable assumption. Table 11 shows the performance gained by our optimal narrow data capture scheduler with refetch replay scheme.... ..."

"... In PAGE 12: ... More details on this approach are provided in [10]. Table4 shows data comparison between our pipelined data cache with bitslicing technique and a conven- tional data cache. The data shown is for 16KB, 4-way cache with 64B blocks.... In PAGE 13: ...the full bits are available are tag comparison and output mux drive. In Table4 , this number, shown in parentheses, is only 0.6ns.... In PAGE 13: ...eeded to access the cache from two cycles into one cycle. Section 5.2 explores the performance benefits that derive from this reduction in cache access latency. Total energy consumption comparison is also shown in Table4 . Our cache consumes 0.... In PAGE 21: ... In this improved refetch replay config- uration, we assume one cycle cache access latency rather than two cycles latency. As shown in Table4 , this is a rea- sonable assumption. Table 11 shows the performance gained by our optimal narrow data capture scheduler with refetch replay scheme.... ..."

"... In PAGE 8: ... A comparison of the corresponding miss ratios is presented in Table 2. From Table 1 and Table2 , it is seen that except patterns 2, 9 and 11, all patterns yield improved performance with the proposed static cache exclusion policy. Sometimes, caching the entire program may be more fruitful than bypassing the cache for part of the program.... In PAGE 8: ... For instance, if there is a sequence such as A10000B10000AB, normal caching would have only 4 misses whereas if A or B is bypassed, approximately half the references will be misses. Two other examples are sequences 2 and 9 in Table2 . Bypassing will be e cient if there are... ..."

"... In PAGE 7: ... A coherence-protocol (based on an exclusive-bit policy plus inclusionbetween L1 and L2) has been included. Table3 shows the port configuration for the different cache models. 4.... ..."

"... In PAGE 9: ... Moreover, this bypassing is simpli ed by the fact that the L1 is write- through, thereby only requiring that MOM memory ac- cesses check the contents of the L1 write bu er when detecting an interference. Table3 shows the port con- guration for the di erent cache models. 4.... ..."

"... In PAGE 7: ... A coherence-protocol (based on an exclusive-bit policy plus inclusionbetween L1 and L2) has been included. Table3 shows the port configuration for the different cache models. 4.... ..."

"... In PAGE 13: ... Although the aggregate miss rates are same for victim and annex caches, the performance is di erent due to the di erence in the number of swaps. This is clear from the total access times presented in Table5 for a miss penalty of 40 cycles. From Table 4 and Table 5, it is seen that except patterns 2, 9 and 11, all patterns yield improved performance with the proposed annex caching policy.... ..."