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Table 5: Compaction Results for GATEST Test Sets

in Fast Algorithms For Static Compaction of Sequential Circuit Test Vectors
by Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel 1997
"... In PAGE 6: ... This is due to fault masking after removal of the inert subsequences, which is assumed not to occur in our implementation of criterion 3. The compaction results for GATEST test sets shown in Table5 display trends similar to the HITEC com- paction results. However, GATEST was targeted at gen- erating compact test sets, and because GATEST test sets are much more compact than HITEC test sets to begin with, less compaction is obtained.... ..."
Cited by 10

Table 4: Compaction Results for HITEC Test Sets

in Fast Algorithms For Static Compaction of Sequential Circuit Test Vectors
by Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel 1997
Cited by 10

Table 6: Compaction Results for DIGATE Test Sets

in Fast Algorithms For Static Compaction of Sequential Circuit Test Vectors
by Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel 1997
Cited by 10

Table 7: Comparing Various Compaction Techniques on HITEC Test Sets Circuit Dynamic compaction Static compaction

in Fast Algorithms For Static Compaction of Sequential Circuit Test Vectors
by Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel 1997
"... In PAGE 7: ... First, the fault coverages obtained are di erent, and second, the execution times needed are also di erent. Table7 compares our results with the static compaction technique proposed in [3] and the dynamic compaction proposed in [11] for the HITEC test sets. Fault coverage, test set size, and time for com- paction are shown for each technique after completion of the compaction.... ..."
Cited by 10

Table 1: Compaction results for HITEC test sets

in State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
by Michael S. Hsiao, Srimat T. Chakradhar, Srimat T. Chakradhar Yy

Table 2: Compaction results for STRATEGATE test sets

in State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
by Michael S. Hsiao, Srimat T. Chakradhar, Srimat T. Chakradhar Yy

Table 6.5. Compaction results for GATTO test sets

in Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams
by Jaan Raik

Table 6.6. Compaction results for SYMBAT test sets

in Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams
by Jaan Raik

Table 6.7. Compaction results for HITEC test sets

in Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams
by Jaan Raik

Table 2: Comparison of Test Set Compactness Number of Vectors

in Putting the Squeeze on Test Sequences
by Elizabeth M. Rudnick, Janak H. Patel 1997
"... In PAGE 6: ... Here, compaction was measured by performing fault simulation using the test set that achieved the higher fault coverage and noting the num- ber of vectors required to achieve the lower fault cover- age. For circuits having differences in fault coverage for the two techniques, the number of vectors needed from each of the test sets to obtain the lower fault coverage is shown in Table2 . Since the test sequences evolved by Squeeze detect more faults than those evolved by GA- COMPACT, fewer faults had to be targeted by the test... ..."
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