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Architectural Description

by Virtex V, Virtex Array , 2002
"... The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic • IOBs provide the interface between the package pins and the CLBs CLB ..."
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for clock-distribution delay compensation and clock domain control • 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load

Stability of Networked Control Systems

by Wei Zhang, Michael S. Branicky, Stephen M. Phillips - IEEE Control Systems Magazine , 2001
"... This article is organized as follows. First, we review some previous work on NCSs and offer some improvements. Then, we summarize the fundamental issues in NCSs and examine them with different underlying network-scheduling protocols. We present NCS models with network-induced delay and analyze their ..."
Abstract - Cited by 315 (8 self) - Add to MetaCart
their stability using stability regions and a hybrid systems technique. Following that, we discuss methods to compensate network-induced delay and present experimental results over a physical network. Then, we model NCSs with packet dropout and multiple-packet transmission as asynchronous dynamical systems (ADSs

Real-Time Control Systems with Delays

by Johan Nilsson, Johan Nilsson , 1998
"... Contents Acknowledgments .......................... 7 1. Introduction ............................ 8 Outline of the Thesis and Publications .............. 9 2. Problem Formulation ....................... 13 2.1 Distributed Control ..................... 13 2.2 Networks ........................... 1 ..."
Abstract - Cited by 191 (2 self) - Add to MetaCart
........................... 18 2.3 Clock Synchronization .................... 20 2.4 RelatedWork......................... 23 3. Modeling of Network Delays .................. 29 3.1 Network Modeled as Constant Delay ........... 29 3.2 Network Modeled as Delays Being Independent ..... 30 3.3 Network Modeled Using Markov Chain

Atomic Broadcast: From Simple Message Diffusion to Byzantine Agreement

by Flaviu Cristian, Houtan Aghili, Ray Strong, Danny Dolev - Information and Computation , 1985
"... In distributed systems subject to random communication delays and component failures, atomic broadcast can be used to implement the abstraction of synchronous replicated storage, a distributed storage that displays the same contents at every correct processor as of any clock time. This paper present ..."
Abstract - Cited by 244 (15 self) - Add to MetaCart
In distributed systems subject to random communication delays and component failures, atomic broadcast can be used to implement the abstraction of synchronous replicated storage, a distributed storage that displays the same contents at every correct processor as of any clock time. This paper

DCS: Distributed Asynchronous Clock Synchronization in Delay Tolerant Networks

by Bong Jun Choi, Student Member, Hao Liang, Student Member, Xuemin (sherman Shen, Weihua Zhuang
"... Abstract—In this paper, we propose a distributed asynchronous clock synchronization (DCS) protocol for Delay Tolerant Networks (DTNs). Different from existing clock synchronization protocols, the proposed DCS protocol can achieve global clock synchronization among mobile nodes within the network ove ..."
Abstract - Cited by 13 (5 self) - Add to MetaCart
Abstract—In this paper, we propose a distributed asynchronous clock synchronization (DCS) protocol for Delay Tolerant Networks (DTNs). Different from existing clock synchronization protocols, the proposed DCS protocol can achieve global clock synchronization among mobile nodes within the network

Reference-Based Clock Distribution Architectures

by Atanu Chattopadhyay
"... Abstract — This paper examines the use of clock distribution architectures employing a reference-based skew compensation technique. For each clock domain, a bi-directional clock line is daisy-chained using specially designed switches at each tap in the distribution. Daisy-chaining the clock decrease ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
Abstract — This paper examines the use of clock distribution architectures employing a reference-based skew compensation technique. For each clock domain, a bi-directional clock line is daisy-chained using specially designed switches at each tap in the distribution. Daisy-chaining the clock

The Timed Asynchronous Distributed System Model

by Flaviu Cristian, Christof Fetzer , 1999
"... We propose a formal definition for the timed asynchronous distributed system model. We present extensive measurements of actual message and process scheduling delays and hardware clock drifts. These measurements confirm that this model adequately describes current distributed systems such as a netwo ..."
Abstract - Cited by 191 (19 self) - Add to MetaCart
We propose a formal definition for the timed asynchronous distributed system model. We present extensive measurements of actual message and process scheduling delays and hardware clock drifts. These measurements confirm that this model adequately describes current distributed systems such as a

Internet Congestion Control.

by Steven H Low , Fernando Paganini , John C Doyle - IEEE Control Systems Magazine, , 2002
"... Abstract This article reviews the current TCP congestion control protocols and overviews recent advances that have brought analytical tools to this problem. We describe an optimization-based framework that provides an interpretation of various flow control mechanisms, in particular, the utility bei ..."
Abstract - Cited by 194 (25 self) - Add to MetaCart
being optimized by the protocol's equilibrium structure. We also look at the dynamics of TCP and employ linear models to exhibit stability limitations in the predominant TCP versions, despite certain built-in compensations for delay. Finally, we present a new protocol that overcomes

Clock Distribution Networks in Synchronous Digital Integrated Circuits

by Eby G. Friedman - Proc. IEEE , 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
Abstract - Cited by 82 (7 self) - Add to MetaCart
parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of high-speed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application

Packet audio playout delay adjustment: performance bounds and algorithms

by Sue B. Moon, Jim Kurose, Don Towsley - ACM/Springer Multimedia Systems , 1998
"... In packet audio applications, packets are buffered at a receiving site and their playout delayed in order to compensate for variable network delays. In this paper, we consider the problem of adaptively adjusting the playout delay in order to keep this delay as small as possible, while at the same ti ..."
Abstract - Cited by 146 (6 self) - Add to MetaCart
In packet audio applications, packets are buffered at a receiving site and their playout delayed in order to compensate for variable network delays. In this paper, we consider the problem of adaptively adjusting the playout delay in order to keep this delay as small as possible, while at the same
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