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The Design and Implementation of Clocked Variables in
"... This paper investigates the addition of Clocked Variables to the X10 Programming Language. Clocked Variables work well for primitives and objects with only primitive fields, but incur substantial performance penalties for more complex objects. We discuss ways to deal with these issues. 1. ..."
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Cited by 1 (0 self)
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This paper investigates the addition of Clocked Variables to the X10 Programming Language. Clocked Variables work well for primitives and objects with only primitive fields, but incur substantial performance penalties for more complex objects. We discuss ways to deal with these issues. 1.
Characterisation of FPGA clock variability
 in Annual Symposium on VLSI, 2008
"... As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic overdesign. A quantified understanding of the contribution different circuit ..."
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Cited by 2 (0 self)
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ferent circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FPGAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from
The Design and Implementation of Clocked Variables in X10
"... This paper investigates the addition of Clocked Variables to the X10 Programming Language. Clocked Variables work well for primitives and objects with only primitive fields, but incur substantial performance penalties for more complex objects. We discuss ways to deal with these issues. ..."
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Cited by 1 (0 self)
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This paper investigates the addition of Clocked Variables to the X10 Programming Language. Clocked Variables work well for primitives and objects with only primitive fields, but incur substantial performance penalties for more complex objects. We discuss ways to deal with these issues.
Reducing the Number of Clock Variables of Timed Automata
 Proc. RTSS'96, 7381, IEEE
, 1996
"... We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks whose values are relevant for the evolution of the system. The second one detects sets of clocks that are always equal. We ..."
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Cited by 77 (7 self)
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We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks whose values are relevant for the evolution of the system. The second one detects sets of clocks that are always equal. We
Symbolic Model Checking for Realtime Systems
 INFORMATION AND COMPUTATION
, 1992
"... We describe finitestate programs over realnumbered time in a guardedcommand language with realvalued clocks or, equivalently, as finite automata with realvalued clocks. Model checking answers the question which states of a realtime program satisfy a branchingtime specification (given in an ..."
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Cited by 578 (50 self)
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in an extension of CTL with clock variables). We develop an algorithm that computes this set of states symbolically as a fixpoint of a functional on state predicates, without constructing the state space. For this purpose, we introduce a calculus on computation trees over realnumbered time. Unfortunately
Realtime System = Discrete System + Clock Variables
 Cornell University
, 1997
"... This paper introduces, gently but rigorously, the clock approach to realtime programming. We present with mathematical precision, assuming no prerequisites other than familiarity with logical and programming notations, the concepts that are necessary for understanding, writing, and executing clock p ..."
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Cited by 33 (6 self)
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This paper introduces, gently but rigorously, the clock approach to realtime programming. We present with mathematical precision, assuming no prerequisites other than familiarity with logical and programming notations, the concepts that are necessary for understanding, writing, and executing clock
A theory of timed automata
, 1999
"... Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of ..."
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Cited by 2651 (32 self)
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using finitely many realvalued clock variables. Automated analysis of timed automata relies on the construction of a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been extensively studied leading to many results establishing connections to circuits
PAML: a program package for phylogenetic analysis by maximum likelihood
 COMPUT APPL BIOSCI 13:555–556
, 1997
"... PAML, currently in version 1.2, is a package of programs for phylogenetic analyses of DNA and protein sequences using the method of maximum likelihood (ML). The programs can be used for (i) maximum likelihood estimation of evolutionary parameters such as branch lengths in a phylogenetic tree, the tr ..."
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Cited by 1459 (17 self)
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, the transition/transversion rate ratio, the shape parameter of the gamma distribution for variable evolutionary rates at sites, and rate parameters for different genes; (ii) likelihood ratio test of hypotheses concerning sequence evolution, such as rate constancy and independence among sites and rate constancy
UPPAAL in a Nutshell
, 1997
"... . This paper presents the overall structure, the design criteria, and the main features of the tool box Uppaal. It gives a detailed user guide which describes how to use the various tools of Uppaal version 2.02 to construct abstract models of a realtime system, to simulate its dynamical behavior, ..."
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Cited by 662 (51 self)
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and verification of realtime systems, based on constraintsolving and onthefly techniques, developed jointly by Uppsala University and Aalborg University. It is appropriate for systems that can be modeled as a collection of nondeterministic processes with finite control structure and realvalued clocks
Razor: A lowpower pipeline based on circuitlevel timing speculation
 in Proc. IEEE/ACM Int. Symp. Microarchitect
, 2003
"... With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systemsonchip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the ..."
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Cited by 288 (8 self)
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With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systemsonchip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain
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