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Table 6.1 Execution Times Comparison (in clock cycles)

in unknown title
by unknown authors

Table 4: Benchmark characteristics for gated clock routing

in Gated Clock Routing Minimizing the Switched Capacitance
by Jaewon Oh And
"... In PAGE 5: ... The instruction stream and the used modules for each instruction are generated according to a probabilistic model of the CPU when it executes typical programs. The benchmark characteristics are shown in Table4 . The length of the instruction stream was 100 thousands for all the benchmarks.... ..."

Table 4: Benchmark characteristics for gated clock routing

in Gated Clock Routing Minimizing the Switched Capacitance
by Jaewon Oh And
"... In PAGE 5: ... The instruction stream and the used modules for each instruction are generated according to a probabilistic model of the CPU when it executes typical programs. The benchmark characteristics are shown in Table4 . The length of the instruction stream was 100 thousands for all the benchmarks.... ..."

Table 4: Benchmark characteristics for gated clock routing

in Gated Clock Routing Minimizing the Switched Capacitance
by Jaewon Oh And
"... In PAGE 5: ... The instruction stream and the used modules for each instruction are generated according to a probabilistic model of the CPU when it executes typical programs. The benchmark characteristics are shown in Table4 . The length of the instruction stream was 100 thousands for all the benchmarks.... ..."

Table III Figure 7. Chip micro photograph To test the chip, four pieces of RG-178 coaxial cable were used as off chip resonators, trimmed to the clock frequency. The test setup consisted of a PCB board with current references, analog single ended to differential drivers and an interface to a logic analyzer. The modulator was tested by applying sinusoidal signals at its input. Here, typically an input frequency of fs/512 was used. The peak SNR occurs for a -4dBfs input. Using a clock generator with a nominal rms jitter of 0.1% the nominal clock period, a SNR of 67dB was measured for an OSR of 128. For this case the measured SNR has been plotted vs. the input signal level in figure 8, which demonstrates a dynamic range of 69 dB.

in A Jitter Insensitive Continuous-Time Σ∆ Σ∆ Modulator Using Transmission Lines
by L. Hernández, P. Rombouts, E. Prefasi, S. Paton, M. Garcia, C. Lopez

Table 2. This chart shows the module level portion of several cases returned during the diagnosis. Nodes G: good B: bad

in An Incremental Retrieval Mechanism for Case-Based Electronic Fault Diagnosis
by Pdraig Cunningham Department, Pdraig Cunningham, Barry Smyth, Andrea Bonzano
"... In PAGE 12: ... Cases matching these function test results are returned from the case-base. In this example these are cases with the signal features shown in Table2 . At this stage the unit under test has not been probed for this signal information so we want the system to ask some discriminating questions - this was the particular strength of the old NODAL system.... In PAGE 13: ....K..... Selecting candidate modules : Retrieved 2 (CLOCK-GENERATOR-1 CLOCK-GENERATOR-2) Validation: The fault is in CLOCK-GENERATOR if N6 is B or N6 is G The 14 cases shown in Table2 are returned and N2 is found to be the first most discriminating criteria. After 6 questions the faulty module is discovered.... ..."

Table 2. This chart shows the module level portion of several cases returned during the diagnosis. Nodes G: good B: bad

in An Incremental Retrieval Mechanism for Case-Based Electronic Fault Diagnosis
by Padraig Cunningham, Barry Smyth, Andrea Bonzano
"... In PAGE 12: ... Cases matching these function test results are returned from the case-base. In this example these are cases with the signal features shown in Table2 . At this stage the unit under test has not been probed for this signal information so we want the system to ask some discriminating questions - this was the particular strength of the old NODAL system.... In PAGE 13: ....K..... Selecting candidate modules : Retrieved 2 (CLOCK-GENERATOR-1 CLOCK-GENERATOR-2) Validation: The fault is in CLOCK-GENERATOR if N6 is B or N6 is G The 14 cases shown in Table2 are returned and N2 is found to be the first most discriminating criteria. After 6 questions the faulty module is discovered.... ..."

Table 5.3: Implementation costs for the Bio-inspired Processing Module. FPGA Block Slice Operating RAM Blocks

in Acknowledgements
by José António, Henriques Germano, Ae Sistemas Electrónicos, Ricardo Manuel, Simões Baptista, Ae Computadores, José António, Henriques Germano, Ricardo Manuel, Simões Baptista 2004

Table 1. Modules of the generation proces

in Architectures for natural language generation: Problems and perspectives
by Koenraad De Smedt, Helmut Horacek, Michael Zock 1996
"... In PAGE 2: ... 2 Some Curent Architectures Traditionaly, the proces of generation is decomposed into two stages which are realized as the main modules in a generation system. Some terms used to label the modules are juxtaposed in Table1 . One module determines the content of an uterance, or what to say.... ..."
Cited by 20

Table 1: Comparison of clock ticks for each module SIMD Method

in An Efficient SIMD-based Quarter-Pixel Interpolation Method for H.264/AVC
by Chae-bong Sohn, Hye-jeong Cho 2006
"... In PAGE 4: ... VTune performance analyzer was used for performance profiling and actual execution time is used for performance evaluation [8]. Table1 presents the numbers of instruction clock ticks of the JM and the proposed methods for the H.264/AVC interpolation.... In PAGE 4: ...IMD 0.055824 0.036922 5.2458 8.9243 According to Table1 , the proposed algorithm would be approximately 5.4 times and 9.... ..."
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