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In Presence of Clock Frequency Offsets

by Sahinoglu Z , 2011
"... Two-way time-of-arrival (TW-ToA) is a ranging protocol that provides distance between two devices in absence of synchronization, but it suffers from range estimation errors when clock frequency offset is present. In this work, we provide a timing counter management scheme for TW-ToA that suppresses ..."
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Two-way time-of-arrival (TW-ToA) is a ranging protocol that provides distance between two devices in absence of synchronization, but it suffers from range estimation errors when clock frequency offset is present. In this work, we provide a timing counter management scheme for TW-ToA that suppresses

The effect of clock frequency offsets on downlink

by Heidi Steendam, Marc Moeneclaey - MC-DS-CDMA”, IEEE, Internal Symposium on Spread Spectrum Techniques and Applications , 2002
"... Abstract- In this contribution, we investigate the effect of clock frequency offsets on the performance of multicarrier direct-sequence CDMA (MC-DS-CDMA) in the downlink, assuming orthogonal spreading sequences. Theoretical expressions are derived for the performance degradation caused by the clock ..."
Abstract - Cited by 6 (0 self) - Add to MetaCart
Abstract- In this contribution, we investigate the effect of clock frequency offsets on the performance of multicarrier direct-sequence CDMA (MC-DS-CDMA) in the downlink, assuming orthogonal spreading sequences. Theoretical expressions are derived for the performance degradation caused by the clock

1Network Clock Frequency Synchronization

by Omer Gurewitz, Israel Cidon, Moshe Sidi
"... The emergence of network convergence emphasizes the need to support distributed synchronous servers such as TDMoIP (pseudo-wire) and 3G cellular gateways over a packet switched infrastructure. Conse-quently, we formalize the problem of network wide clock frequency synchronization and introduce novel ..."
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The emergence of network convergence emphasizes the need to support distributed synchronous servers such as TDMoIP (pseudo-wire) and 3G cellular gateways over a packet switched infrastructure. Conse-quently, we formalize the problem of network wide clock frequency synchronization and introduce

Clock-Frequency Assignment for Multiple Clock Domain

by unknown authors
"... Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can be customized, the number of unique clock frequencies on a platform is typically limited. We define the clock-frequency ..."
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Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can be customized, the number of unique clock frequencies on a platform is typically limited. We define the clock-frequency

queue: Customized large-scale clock frequency scaling

by Ananta Tiwari , Michael Laurenzano , Joshua Peraza , Laura Carrington , Allan Snavely - Proceedings of the Second International Conference on Cloud and Green Computing, CGC ’12 , 2012
"... Abstract-We examine the scalability of a set of techniques related to Dynamic Voltage-Frequency Scaling (DVFS) on HPC systems to reduce the energy consumption of scientific applications through an application-aware analysis and runtime framework, Green Queue. Green Queue supports making CPU clock f ..."
Abstract - Cited by 2 (2 self) - Add to MetaCart
Abstract-We examine the scalability of a set of techniques related to Dynamic Voltage-Frequency Scaling (DVFS) on HPC systems to reduce the energy consumption of scientific applications through an application-aware analysis and runtime framework, Green Queue. Green Queue supports making CPU clock

HDL-synthesizable dynamic clock frequency controller with hybrid

by Robert M. Senger, Eric D. Marsman - LC clocking,” Intl. Symp. on Circuits and Systems (ISCAS , 2006
"... Abstract—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully integrated hybrid temperature-compensated LC oscillator (TC-LCO) and ring oscillator clock reference avoids PLL lock ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Abstract—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully integrated hybrid temperature-compensated LC oscillator (TC-LCO) and ring oscillator clock reference avoids PLL

Meindl, “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution

by Keith A. Bowman, Steven G. Duvall, James D. Meindl, Life Fellow - in IEEE ISSCC Dig. Tech. Papers , 2001
"... Abstract—A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25- m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations ..."
Abstract - Cited by 182 (2 self) - Add to MetaCart
Abstract—A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25- m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within

1Asynchronous Source Clock Frequency Recovery through Aperiodic Packet Streams

by Kyeong Soo Kim
"... Abstract—We consider the most general case of source clock frequency recovery (SCFR) in packet networks, i.e., asyn-chronous SCFR through aperiodic packet streams, where there is neither a common reference clock nor any relation between packet generation intervals and a source clock frequency. We fo ..."
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Abstract—We consider the most general case of source clock frequency recovery (SCFR) in packet networks, i.e., asyn-chronous SCFR through aperiodic packet streams, where there is neither a common reference clock nor any relation between packet generation intervals and a source clock frequency. We

Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip

by Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid
"... Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can be customized, the number of unique clock frequencies on a platform is typically limited. We define the clock-frequency ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can be customized, the number of unique clock frequencies on a platform is typically limited. We define the clock-frequency

UPLINK AND DOWNLINK MC-DS-CDMA SENSITIVITY TO STATIC CLOCK FREQUENCY OFFSETS

by unknown authors
"... Abstract- We study the effect of fixed clock frequency offsets on the performance of multicarrier direct-sequence CDMA (MC-DS-CDMA) for both uplink and downlink communication, assuming orthogonal spreading sequences. We show that for both uplink and downlink MC-DS-CDMA, the performance in the presen ..."
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Abstract- We study the effect of fixed clock frequency offsets on the performance of multicarrier direct-sequence CDMA (MC-DS-CDMA) for both uplink and downlink communication, assuming orthogonal spreading sequences. We show that for both uplink and downlink MC-DS-CDMA, the performance
Results 1 - 10 of 57,279