Results 1 - 10 of 34,101

Table 2: Clock Domain Analysis

in Abstract Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
by Nisar Ahmed, Mohammad Tehranipoor
"... In PAGE 3: ...of controlled scan flip-flops is referred to as the dominant clock do- main. Table2 shows the number of scan flip-flops in each of the six clock domains. It can be noticed that clkA clock domain is the dom- inant clock domain with approximately 18K scan flip-flops.... ..."

Table 2. FIFO buffer model.

in A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
by Hang-sheng Wang, Li-shiuan Peh, Sharad Malik
"... In PAGE 2: ... For instance, a FIFO buffer does not need a decoder. Figure 1 (next page) sketches the structure of a FIFO buffer, and Table2 lists the model parameters and equations. Crossbar switch.... ..."

Table 1. Buffered MINs and their control strategies.

in Performance Study of Packet Switching Multistage Interconnection Networks
by Jungsun Kim
"... In PAGE 3: ...ause of a network conflict, i.e., other packets compete for the same output link of an SE or because of a full buffer at the next stage. We analyze and compare four representa- tive buffered MINs in Table1 . The networks are illustratedin Fig.... ..."

Table 4. 1 Control buffer for a write trans Table 4. 2 Control buffer for a read trans.

in Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques
by Aristides A. Nikologiannis 2001
"... In PAGE 63: ... addr. Write address (from PWT entry indexed by transit_id) Table4 . 3 Control buffer for free list update (write transaction) 4.... In PAGE 67: ... Read address field (from the pipeline buffer) read addr. Read address field (from the pipeline buffer) Table4 . 4 Control buffer Table 4.... In PAGE 67: ... Read address field (from the pipeline buffer) Table 4. 4 Control buffer Table4 . 5 Control buffer 4.... In PAGE 71: ...ncoming requests. The FSM of our arbiter is illustrated in the table 4.6. Table4 . 6 The Arbiter FSM 4.... ..."
Cited by 7

Table 7: Test, Clock, and Idle Controls

in unknown title
by unknown authors 1996

Table 4.3: State transition table of the memory access controller.

in for the MOVE processor
by Kang Laboratory Of, I. Kang, I. Kang, Mentor Ir, R. Lamberts

Table 7.1. Example of time between slips in an AAL1 buffer due to synchronization fractional frequency offsets (i.e., clocks in holdover or free-run) when using SRTS 7.3.2 Use of Adaptive Clock Recovery Techniques 7.3.3 Use of Controlled Slip Mechanism in AAL Type 1 7.3.4 Use of AAL Type 1 Receiver Buffer Recentering Heuristics 7.3.5 DS1 and DS3 Jitter 7.3.6 DS1 and DS3 Wander

in Timing on CBR Service Clock Recovery . . .
by G. Garner

Table 7.1. Example of time between slips in an AAL1 buffer due to synchronization fractional frequency offsets (i.e., clocks in holdover or free-run) when using SRTS 7.3.2 Use of Adaptive Clock Recovery Techniques 7.3.3 Use of Controlled Slip Mechanism in AAL Type 1 7.3.4 Use of AAL Type 1 Receiver Buffer Recentering Heuristics 7.3.5 DS1 and DS3 Jitter

in ATM Network Timing on CBR Service Clock Recovery and Synchronization
by Timing On Cbr

Table 2 End-to-End Delay, Bound Delay, Delay-Jitter, and Buffer Space Requirements

in Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks
by Hui Zhang 1995
"... In PAGE 11: ... To prevent packet loss, we assume buffer space is allocated on a per connection basis at each server during connection establishment time. Table2 presents the end-to-end characteristics and buffer space requirement of a connection when different work- conserving service disciplines are used. The table can be interpreted as the following.... In PAGE 17: ... It can be shown that the following holds According to Table 4, an end-to-end delay bound of can be provided to the connection + ET=, P3 in both cases. Compared to Table2 , the above delay bound is identical to that provided by WFQ, WF2Q, and virtual clock servers. The about assignments are just examples to illustrate the flexibility of rate-controlled service disciplines.... ..."
Cited by 449

Table 11: Performance of buffer-based congestion control

in Delivery of On-Demand Video Services in Rural Areas via
by Odd Inge Hillestad, Andrew Perkis 2006
"... In PAGE 8: ... To illustrate the equalization of buffer occupancy, simulations were performed in which all users request the same video clip, namely STEM C2 . It can be seen from Table11 that the clients using the same coding and modulation scheme, thus sharing a single buffer in the BS, receives very similar average buffer fullness. One issue with this approach is that the reaction time of the system is dependent on the client buffer size: a system with a larger buffer will react less quickly than one with a smaller buffer.... ..."
Cited by 3
Results 1 - 10 of 34,101