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Results 11 - 20
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111
An embedded true random number generator for FPGAs
- In ACM FPGA ’04
, 2004
"... Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter a ..."
Abstract
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Cited by 41 (0 self)
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and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good
Fast module mapping and placement for datapaths in FPGAs
- Proceedings of the International Symposium on Field Programmable Gate Arrays
, 1998
"... Abstract By tailoring a compiler tree-parsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure; this allows exploitation of specialized datapath features in ..."
Abstract
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Cited by 51 (2 self)
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module mapping. Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity. Background Field programmable gate arrays (FPGAs) consist of configurable logic blocks (CLBs), usually arranged in a 2-dimensional grid, connected by a
Design Methodology for Fine-Grained Leakage Control
- in MTCMOS”, International Symposium on Low Power Electronics and Design
, 2003
"... Abstract Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enable ..."
Abstract
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Cited by 40 (3 self)
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that reduce leakage in active CLBs by up to 2.2X (measured) for some CLB configurations.
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
, 1998
"... The logic blocks #CLBs# of a lookup table #LUT# based FPGA consist of one or more LUTs, possibly of di#erent sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two di#erent sizes #called ICLBs#. The Actel ES6500 family is an example of a class of commercia ..."
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Cited by 4 (0 self)
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The logic blocks #CLBs# of a lookup table #LUT# based FPGA consist of one or more LUTs, possibly of di#erent sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two di#erent sizes #called ICLBs#. The Actel ES6500 family is an example of a class
Achieving Better Load Balance in Distributed Storage System
- In International Conference on Parallel and Distributed Processing Techniques and Applications
, 2002
"... The CPU processing speed and disk capacity are increasing tremendously during the past decade. However, the even faster increasing number of users generates higher requirements for high performance and huge capacity computer systems. More and more applications are now running on distributed systems. ..."
Abstract
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Cited by 1 (0 self)
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. Load balance is an important issue in distributed storage systems. Currently, very few of them has a finelytuned load balance scheme to achieve higher system throughput and shorter client response times. We propose a new load balance scheme called Cooperative Load Balance Scheme (CLBS) to solve
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
, 1998
"... The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ICLBs). The Actel ES6500 family is an example of a class of commerc ..."
Abstract
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The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ICLBs). The Actel ES6500 family is an example of a class
Built-In Self-Test of Configurable Logic Blocks in
"... Abstract — A Built-In Self-Test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of opera ..."
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Abstract — A Built-In Self-Test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes
The therapeutic potential of bacteriocins as protein antibiotics
"... The growing incidence of antibiotic-resistant Gram-negative bacterial infections poses a serious threat to public health. Molecules that have yet to be exploited as antibiotics are potent protein toxins called bacteriocins that are produced by Gram-negative bacteria during competition for ecologica ..."
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for ecological niches. This review discusses the state of the art regarding the use for therapeutic purposes of two types of Gram-negative bacteriocins: colicin-like bacteriocins (CLBs) and tailocins. In addition to in vitro data, the potency of eight identified CLBs or tailocins has been demonstrated in diverse
FAST: FPGA Targeted RTL Structure Synthesis Technique
"... In this paper we present an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from boolean networks. Each component part consists of single-hit or multi-bit slice of one or more closely connected RTL components and are realized using one ..."
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one or more CLBs. For Otis mapping onto CLBs, primarily function decomposition is employed. Conditions for some decompositions, disjunctive as well as non-disjunctive, useful in the FPGA context have been derived. As decomposition is a computation intensive process, some necessary conditions which
Accurate Area and Delay Estimators for FPGAs
- PROC. DESIGN AUTOMATION AND TEST IN
, 2002
"... We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic design space exploration to synthesize hardware for a Field Programmable Gate Array (FPGA) which meets the user area and fr ..."
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Cited by 18 (2 self)
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and frequency specifications. We present an area estimator which is used to estimate the maximum number of Configurable Logic Blocks (CLBs) consumed by the hardware synthesized for the Xilinx XC4010 from the input MATLAB algorithm. We also present a delay estimator which finds out the delay in the logic
Results 11 - 20
of
111
