### Table 1. Experimental Results showing the percentage error in area estimation Benchmarks Estimated CLBs Actual CLBs % Error in Estimation

2002

Cited by 8

### Table 1: Distributions of literals to CLBs (a) equiprobable (b) measured from 1271 CLBs, 60 designs.

1991

Cited by 14

### Table 1. Implementation results for the 3x3 convolution coprocessor

1999

"... In PAGE 17: ... The next section presents two important improvement strategies, in order to reduce the complexity of our three basic architectures. 4 COMPLEXITY REDUCTION STRATEGIES The values contained in Table 2, which expand in more detail the previous results in Table1 , will serve as a reference for estimating the effectiveness of the cost reduction strategies applicable to the architecture presented in the previous section. This complexity analysis is presented in terms of transistor count for a standard cell implementation, since the sharing phenomenon in Xilinx FPGAs introduces variance in the number of CLB.... ..."

Cited by 3

### Table 4: Number of used CLBs of Xilinx XC4000 FPGAs (Notation: F20D90 means lter pole-angle 20:00 delay Comb D = 90). Total Practice: 1572 CLBs. Total non- recursive FIR: 11292 CLBs.

1997

Cited by 5

### TABLE A.I A comparison between FPGA implementations of various algorithms

### Table 1 reports the preliminary results we have obtained using our algorithm. In particular, columns CLBs, PI and PO report the number of CLBs, primary inputs and primary outputs of the circuit. Columns Initial and Final give the power dissipation of the circuit before and after optimization. Column #CLBs tells the number of CLBs that have been re-programmed, column % gives the percentage power reduction, and column Time indicates the CPU time, measured in in seconds on a 200MHz Pentium Pro Linux machine with 128MB of memory, required by the algorithm to complete.

"... In PAGE 14: ... Table1 : Power Optimization Results. On all the benchmarks, power was estimated by using both zero-delay and real-delay simulation.... In PAGE 15: ...From Table1 it is interesting to note that the decrease in power dissipation is substantial for larger circuits. This reinforces our claim that there are many degrees of freedom available to explore in large circuits.... ..."

### Table 1 The number of CLBs used of FPGA

2002

Cited by 1

### Table 3: CLBs required for mapping the circuits

### TABLE III Number of CLBs needed for registers

### Table 2. Number of CLBs, Flip-Flops and Maximum frequency (MHz)

"... In PAGE 7: ... Table2 shows the number of CLBs and the maximum clock frequency (in Megahertzs). The total number of clock cycles is equal to n in the case of the Shift and Add and Montgomery multipliers, and equal to 2.... ..."