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Table 3 Primary language instruction 1998 and 1999 for districts in three categories of commitment to primary language programs prior to Proposition 227

in unknown title
by unknown authors 2000
Cited by 2

Table 1. Instruction-level measurements on the index server.

in unknown title
by unknown authors
"... In PAGE 5: ... The main activity in the index server consists of decoding compressed information in the inverted index and finding matches against a set of documents that could satisfy a query. Table1 shows some basic instruction-level measurements of the index server program running on a 1-GHz dual- processor Pentium III system. The application has a moderately high CPI, considering that the Pentium III is capable of issuing three instructions per cycle.... In PAGE 6: ... The avail- able thread-level parallelism should allow near-linear speedup with the number of cores, and a shared L2 cache of reasonable size would speed up interprocessor communication. Memory system Table1 also outlines the main memory sys- tem performance parameters. We observe good performance for the instruction cache and instruction translation look-aside buffer, a result of the relatively small inner-loop code size.... ..."

Table 1. Instruction-level measurements on the index server.

in AMENABLE TO EXTENSIVE PARALLELIZATION, GOOGLE’S WEB SEARCH APPLICATION LETS DIFFERENT QUERIES RUN ON DIFFERENT PROCESSORS AND, BY PARTITIONING THE OVERALL INDEX, ALSO LETS A SINGLE QUERY USE MULTIPLE PROCESSORS. TO HANDLE THIS WORKLOAD, GOOGLE’S ARCHITECT
by Luiz André Barroso, Jeffrey Dean, Urs Hölzle, Superior Performance, At A Fraction, Of The, Cost Of, A System Built
"... In PAGE 5: ... The main activity in the index server consists of decoding compressed information in the inverted index and finding matches against a set of documents that could satisfy a query. Table1 shows some basic instruction-level measurements of the index server program running on a 1-GHz dual- processor Pentium III system. The application has a moderately high CPI, considering that the Pentium III is capable of issuing three instructions per cycle.... In PAGE 6: ... The avail- able thread-level parallelism should allow near-linear speedup with the number of cores, and a shared L2 cache of reasonable size would speed up interprocessor communication. Memory system Table1 also outlines the main memory sys- tem performance parameters. We observe good performance for the instruction cache and instruction translation look-aside buffer, a result of the relatively small inner-loop code size.... ..."

Table 1. Summary statistics of response times for the scale change metaphor

in Evaluating the Usability of the Scale Metaphor for Querying Semantic Spaces
by Sara Irina Fabrikant 2001
Cited by 6

Table 2: Summary of the mean mental effort dataa Supportive information Before During

in Overige leden beoordelingscommissie:
by Druk Datawyse Maastricht, Omslag Yvo De Ruiter, Liesbeth Kester, Liesbeth Kester
"... In PAGE 55: ...D = 17.91; p lt; 0.01). For an overview of the results see table 2. Table2 : Mean total time (min) spent on the practice problems and the apos;before apos; information block Supportive information Before During Procedural information M SD n M SD n Before 40.21 10.... In PAGE 70: ... Test problems For an overview of the test results see Table 2. Table2 : Overview of the mean test results. Information presentation format Variable Split-source Integrated M SD N M SD N Test scores (max.... In PAGE 82: ... ANOVA revealed no differences between experimental groups for the use of the repeat button during practice. Test problems See Table2 for an overview of the results for the test problems. ... In PAGE 83: ... Table2 : Overview of Results for the Test Problems. Information Presentation Formata SupB-ProcD SupB-ProcB SupD-ProcD SupD-ProcB M SD M SD M SD M SD Transfer test problems Transfer test performance* (Max.... ..."

Table 1. t-Test Results for Writing Performance Scores in Each Instruction Method

in unknown title
by unknown authors 2007
"... In PAGE 7: ...ontrol group; t = -7.23, p lt; .001 and the experimental group; t = -7.47, p lt; .001 (see Table1 ). As shown in Table 1, the control group increased their test scores from a pretest score mean of 65.... ..."

Table 3. t-Test Results for Writing Apprehension Scores in Each Instruction Method

in unknown title
by unknown authors 2007
"... In PAGE 9: ...oth the control group, t = 4.37, p lt; .001, and the experimental group, t = 2.94, p lt; .01 (see Table3 ). Table 3 also shows that the control group had decreased test scores, from a pretest score mean of 89.... ..."

Table 3. Sample program for case 3.*

in Microcode Processing: Positioning and Directions
by Vassiliadis, Stephan Wong, Sorin Cotofana
"... In PAGE 5: ...architecture that will allow combining mul- tiple instructions and executing them in par- allel.6,7,8 You could then rewrite the move character program as in Table3 . The program assumes five instruction slots for different instructions: one slot for load/store instruc- tions, two slots for integer instructions, one slot for floating-point instructions, and one slot for branch instructions.... ..."

Table 1. Features of RISC Architecture

in unknown title
by unknown authors

Table 1. Features of RISC Architecture

in unknown title
by unknown authors
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