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circuit size in the exponential hierarchy
, 1999
"... Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS ..."
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Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS
Circuit size relative to pseudorandom oracles
 THEORETICAL COMPUTER SCIENCE A 107
, 1993
"... Circuitsize complexity is compared with deterministic and nondeterministic time complexity in the presence of pseudorandom oracles. The following separations are shown to hold relative to every pspacerandom oracle A, and relative toalmost every oracle A 2 ESPACE. (i) NP A is not contained in SIZE ..."
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Cited by 17 (4 self)
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Circuitsize complexity is compared with deterministic and nondeterministic time complexity in the presence of pseudorandom oracles. The following separations are shown to hold relative to every pspacerandom oracle A, and relative toalmost every oracle A 2 ESPACE. (i) NP A is not contained in SIZE
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
The Minimum Oracle Circuit Size Problem
, 2014
"... We consider variants of the Minimum Circuit Size Problem MCSP, where the goal is to minimize the size of oracle circuits computing a given function. When the oracle is QBF, the resulting problem MCSPQBF is known to be complete for PSPACE under ZPP reductions. We show that it is not complete under lo ..."
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We consider variants of the Minimum Circuit Size Problem MCSP, where the goal is to minimize the size of oracle circuits computing a given function. When the oracle is QBF, the resulting problem MCSPQBF is known to be complete for PSPACE under ZPP reductions. We show that it is not complete under
Characterizing nondeterministic circuit size
 In Proceedings of the 25th STOC
, 1993
"... Consider the following simple communication problem. Fix a universe U and a family Ω of subsets of U. Players I and II receive, respectively, an element a ∈ U and a subset A ∈ Ω. Their task is to find a subset B of U such that A∩B  is even and a ∈ B. With every Boolean function f we associate a co ..."
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Cited by 10 (4 self)
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collection Ωf of subsets of U = f −1 (0), and prove that its (one round) communication complexity completely determines the size of the smallest nondeterministic circuit for f. We propose a linear algebraic variant to the general approximation method of Razborov, which has exponentially smaller description
HEURISTIC APPROACH TO CIRCUIT SIZING PROBLEM
"... Abstract: Circuit sizing problem in application specific analog integrated circuit design is in most cases limited to setting MOSFET channel widths and lengths. It is usually performed by hand by an experienced human designer. As the circuit sizing is an optimization process by its nature, optimizat ..."
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Abstract: Circuit sizing problem in application specific analog integrated circuit design is in most cases limited to setting MOSFET channel widths and lengths. It is usually performed by hand by an experienced human designer. As the circuit sizing is an optimization process by its nature
LowPower CMOS Digital Design
 JOURNAL OF SOLIDSTATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413
, 1992
"... Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use the ..."
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Cited by 570 (20 self)
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Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use
Wattch: A Framework for ArchitecturalLevel Power Analysis and Optimizations
 In Proceedings of the 27th Annual International Symposium on Computer Architecture
, 2000
"... Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high ..."
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Cited by 1295 (43 self)
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Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve
Route Packets, Not Wires: OnChip Interconnection Networks
, 2001
"... Using onchip interconnection networks in place of adhoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structur ..."
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Cited by 864 (10 self)
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. The structured network wiring gives wellcontrolled electrical parameters that eliminate timing iterations and enable the use of highperformance circuits to reduce latency and increase bandwidth. The area overhead required to implement an onchip network is modest, we estimate 6.6%. This paper introduces
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