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Tables Cell Layouts

in Testing CMOS Logic Gates for Realistic Shorts
by Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee

Table 2 - Manual Cell Layouts

in Design, Layout and Verification of an FPGA using Automated Tools
by unknown authors
"... In PAGE 5: ... However, it is possible that tools such as Cadabra from Synopsys [30] could be used for this step in the future. The fifteen cells required for the design are listed in Table2 . All the cells are relatively small in size ranging from an inverter with two transistors to a group of SRAM bits requiring eighty transistors.... ..."

Table I City Area Cell Layout with 100 cells

in AN EFFICIENT SEQUENTIAL PAGING TECHNIQUE USING FEEDBACK STRATEGY N. Banerjee*, D. Saha*, P. S. Bhattacharya
by And Mukherjee Department, N. Banerjee, D. Saha, P. S. Bhattacharya, A. Mukherjee

Table 1: Tactical vs. generic standard cell layouts

in An Improved “Soft ” eFPGA Design and Implementation Strategy
by Guy Lemieux, Resve Saleh
"... In PAGE 3: ... Figure 4: Cell area distribution in island-style eFPGA Figure 5: Area savings due to tactical standard cells Custom layouts were created for 3, 4, and 5-input LUTs, SRAMs, and multiplexers. Table1 compares these with their generic standard cell equivalents (LUT area includes SRAMs). The results show area savings of 2.... ..."

TABLE I THE BENCHMARK CIRCUITS FOR THE MACRO-CELL LAYOUT GENERATION PROBLEM

in Hybrid Genetic Algorithms for Constrained Placement Problems
by Volker Schnecke, Oliver Vornberger

TABLE X COMPARISON OF TWO MEMORY CELL LAYOUTS Characteristic Cell #1 Cell #2

in Final Report EECS 425: Integrated Circuits Laboratory Winter 1995
by Wi Nt Er, Alejandro F. González

Table 6 shows the densities directly evaluated on standard-cell layout (processes ECPD07 and

in unknown title
by unknown authors
"... In PAGE 7: ...TR# Density CELL TR# Density INV 2 3008 an02d0 6 46875 NAND2 4 5906 an13d1 10 44643 AOI22 8 11363 an04d2 12 53571 AND4 10 12449 aor21d4 14 48611 DFF 29 14441 nr02d4 16 71429 aoi222d2 18 56250 lachq1 20 48077 aoi2222d2 24 57692 dfnrb1 26 42763 labhb1 28 51471 xr03d4 28 58333 dfcrn2 30 49342 denrq1 34 53125 jkbrb2 46 53241 sdbrb2 52 56034 Table6 - Standard-cell densities, process ECPD07 and ECAT05 Table 7 shows the densities obtained for circuits generated with standard-cells, using place and route tools. The routing area for these circuits corresponds to 56% of the total area, close to the predicted values.... ..."

Table1: Critical charge from SPICE simulations for hits on nodes A and B. The transition refers to the output of the cell, and SA stands for Sensitive Area as measured from the cell layout.

in Single Event Effects in Static and Dynamic Registers in a 0.25m CMOS Technology
by Faccio Kloukinas Marchioro, F. Faccio, K. Kloukinas, A. Marchioro, T. Calin, J. Cosculluela, M. Nicolaidis, R. Velazco 1999
"... In PAGE 4: ...The critical charge computed from the SPICE simulation is reported in Table1 , which also indicates the sensitive area SA (or cross-section) of the cell estimated from the layout for hits in both A and B and for 0- gt;1 and 1- gt;0 transitions. In the estimate from the layout, the sensitive area has been taken as the drain diffusion area of the inverter transistors and the source and drain diffusion areas of the switches.... ..."
Cited by 5

Table 2. Layout modification Results for Standard-Cell Blocks.

in Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Abstract
by Resolution Enhancement Technology (ret
"... In PAGE 6: ... 5.2 Phase Conflict Correction Results Table2 reports the results of using the proposed layout mod- ification scheme for correcting the phase conflicts chosen by the detection step on the same layouts. Column Area reports the area of the designs in square microns.... ..."

TABLE II LAYOUT MODIFICATION RESULTS FOR STANDARD-CELL BLOCKS.

in Fast and efficient bright-field AAPSM conflict detection and correction
by C. Chiang, A. B. Kahng, S. Sinha, X. Xu, A. Z. Zelikovsky
Cited by 1
Results 1 - 10 of 10,385