### Table 14: Comparison of modular multiplication delays.

"... In PAGE 8: ...able 13: Comparison of area-time efficiency of modular reduction..........................77 Table14 : Comparison of modular multiplication delays.... In PAGE 88: ...77 0.40 Table14 gives the results of the comparison of the time to perform modular multiplication using existing processors listed in Table 10. Table 14: Comparison of modular multiplication delays.... In PAGE 88: ...bitwidth processors were providedin [28] and used here. The results in Table14 indicate that our implementation is faster than all modular multipliers except for the one by McIvor [32]. Thier multiplier, however, ignores the cost ... ..."

### Table 3: Average number of equivalent 32-bit operations per vertex coordinate for appropriate output precision

"... In PAGE 9: ... The leftmost column indicates the number of bits that are required in the output display. Table3 shows the average number of equivalent 32-bit opera- tions per vertex during the transformations while exploiting spatial and temporal coherences. Central to this idea is that one 32-bit operation is equivalent to two 16-bit, four 8-bit, and eight 4-bit op- erations.... ..."

### Table 3: Number of one bit XOR operations for different factor bit lengths and with different multiplication methods

"... In PAGE 3: ... In [14] the bit complexities of CKM were determined. Their results together with the complexities for the CPM and RAIK are shown in Table3 . RAIK requires the same number of AND operations as CKM, while the XOR op- erations are about 10% less.... In PAGE 3: ... Instead, the recursion is truncated, preferable at bit size n = 4, and the small partial multiplication is per- formed by CPM. Corresponding to Table3 the hybrid CKM (hCKM) substitutes 24 XORs and 9 ANDs for 9 XORs and 16 ANDs for every 4 bit leaf multiplication, i.e.... ..."

### Table 6: Operation sequence for a -bit word

"... In PAGE 6: ... All CF- dsts between are detected, where . Table 5 and Table6 show respectively the DBS and the operation sequence for -bit words, requiring only Level 0 and Level 1 operations as discussed above. The required number of DBs ( ) to sensitize all CFdsts within -bit words is: 6 the used in Level 0 + 3 the used in the other levels the number of levels = 3 + 3 ; which is identical to the of CFids.... In PAGE 7: ... 3. For CFdsts: , whereby the DBOS (consisting of the operations together with the DBs) is taken from Table6 (for ). The above intra-word test may be modified as follows without any impact on the fault coverage: 1.... ..."

### Table 1: Static resource consumption for each benchmark. Some resources are expressed in units, while other are expressed in bit-operations.

"... In PAGE 8: ... We analyze a set of programs from the Mediabench [17] and SpecInt95 [28] benchmark suites. Resources: Table1 displays the resources required for the complete implementation of these programs in hard- ware. We do not include in these numbers the standard library or the operating system kernel.... In PAGE 8: ... We report for these just total counts. The columns in Table1 are: LOC: lines of source code, including whitespace and comments, before preprocessing SAMs: number of SAMs generated fp: floating-point operations memory: load and store operations call/ret: call and return operations predicates: boolean operations computing predicates (all of them are binary or unary, so each is one oper- ation) arithmetic: estimated number of operations necessary to implement the integer arithmetic operations (con- stant multipliers are strength-reduced to a few addi- tions; non-constant multiplies and divisions are as- sumed to use D2BE bits, where D2 is the input width) mux: number of bit operations in multiplexors (number of inputs * input size) loop regs: number of bits in loop registers Comments: The raw computation resources required (the total of the bits columns) is below 2 million for all 0 200 400 600 800 1000 1200 1400 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 Operations Circuit number quot;ops-inline quot; quot;ops-noinline quot; Figure 8: Operations in each SAM, with and without pro- cedure inlining. The data is for all the SAMs synthesized from all our benchmarks.... ..."

Cited by 3

### Table 1: Static resource consumption for each benchmark. Some resources are expressed in units, while other are expressed in bit-operations.

"... In PAGE 8: ... We analyze a set of programs from the Mediabench [17] and SpecInt95 [28] benchmark suites. Resources: Table1 displays the resources required for the complete implementation of these programs in hard- ware. We do not include in these numbers the standard library or the operating system kernel.... In PAGE 8: ... We report for these just total counts. The columns in Table1 are: LOC: lines of source code, including whitespace and comments, before preprocessing SAMs: number of SAMs generated fp: floating-point operations memory: load and store operations call/ret: call and return operations predicates: boolean operations computing predicates (all of them are binary or unary, so each is one oper- ation) arithmetic: estimated number of operations necessary to implement the integer arithmetic operations (con- stant multipliers are strength-reduced to a few addi- tions; non-constant multiplies and divisions are as- sumed to use D2 BE bits, where D2 is the input width) mux: number of bit operations in multiplexors (number of inputs * input size) loop regs: number of bits in loop registers Comments: The raw computation resources required (the total of the bits columns) is below 2 million for all 0 200 400 600 800 1000 1200 1400 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 Operations Circuit number quot;ops-inline quot; quot;ops-noinline quot; Figure 8: Operations in each SAM, with and without pro- cedure inlining. The data is for all the SAMs synthesized from all our benchmarks.... ..."

### Table 7: Timings (in milliseconds) for 1024-bit and 2048-bit RSA operations on various platforms.

2000

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### Table 4 - DS1 Synchronization Codewords (Second Generation Synchronization Status

"... In PAGE 19: ... 10.4 DS1 Message Content The synchronization status messages are transmitted using the bit-patterned messages in the DS1 ESF data link, and are shown in Table 2 for first generation synchronization status messaging and in Table4 for second generation synchronization status messaging. 10.... ..."