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An efficient algorithm for exploiting multiple arithmetic units
 IBM JOURNAL OF RESEARCH AND DEVELOPMENT
, 1967
"... This paper describes the methods employed in the floatingpoint area of the System/360 Model 91 to exploit the existence of multiple execution units. Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions ..."
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Cited by 391 (1 self)
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optimizes the program execution on a local basis. The application of these techniques is not limited to floatingpoint arithmetic or System/360 architecture. It may be used in almost any computer having multiple execution units and one or more 'accumulators.' Both of the execution units, as well
VHDL Library of Arithmetic Units
 in Proc. First Int. Forum on Design Languages (FDL’98
, 1998
"... A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural VHD ..."
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Cited by 12 (3 self)
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A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural
VHDL Library of Arithmetic Units
, 1998
"... A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural VHD ..."
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A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural
Point Arithmetic Unit
, 1985
"... for the Degree of Master of Science. This thesis presents a case study in the procedural design of the layout of a complex digital circuit. This is the task of writing a program which constructs a VLSI circuit layout given a set of variable parameters which specify the desired functionality of the c ..."
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are free of critical race conditions and chargesharing problems. As an example, we carry out the creation of a program for building a floatingpoint addition unit which has selectable number of bits of exponent and fraction in the floatingpoint representation. The highlevel design of a companion floating
Arithmetic Unit Based on Continued Fraction
 TO APPEAR IN PROCEEDINGS OF ECI’2006 CONFERENCE
, 2006
"... We introduce architecture of an arithmetic unit that is based on continued fractions and allows computing any linear rational function of two variables, including basic arithmetic operations like addition, subtraction, multiplication and division. Such a unit can easily exploit the parallel nature o ..."
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Cited by 2 (1 self)
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We introduce architecture of an arithmetic unit that is based on continued fractions and allows computing any linear rational function of two variables, including basic arithmetic operations like addition, subtraction, multiplication and division. Such a unit can easily exploit the parallel nature
Implementing and Evaluating Adiabatic Arithmetic Units
 In IEEE 1996 Custom Integrated Circuit Conference
, 1996
"... In recent years, several adiabatic logic architectures have been proposed for lowpower VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of low ..."
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Cited by 7 (3 self)
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of lowpower arithmetic units. We investigated implementation issues specific to adiabatic system development and performed a systematic comparison of our designs with corresponding CMOS circuits. In this paper we describe our adiabatic designs, discuss implementation issues at the logic
Rational Arithmetic Units In Computer Systems
, 2000
"... Computer arithmetic remains important as we move to systemsonachip that dedicate large areas for specialpurpose arithmetic units. System application areas such as signal processing, multimedia, and mobile computing require the evaluation of functions as fast as possible with as little power as p ..."
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Cited by 4 (3 self)
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Computer arithmetic remains important as we move to systemsonachip that dedicate large areas for specialpurpose arithmetic units. System application areas such as signal processing, multimedia, and mobile computing require the evaluation of functions as fast as possible with as little power
EFFICIENT MODULAR ARITHMETIC UNITS FOR LOW POWER CRYPTOGRAPHIC APPLICATIONS
"... Efficient modular arithmetic units for low power ..."
AllOptical Arithmetic Unit Based On The Hardlimiters
"... Abstract: The paper describes the design of all optical parallel adder and all optical arithmetic unit by using of a set of optical full adders and hardlimiters. The parallel adder and arithmetic unit are demonstrated via simulations and experiments. The optical Arithmetic unit can be used to perf ..."
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Abstract: The paper describes the design of all optical parallel adder and all optical arithmetic unit by using of a set of optical full adders and hardlimiters. The parallel adder and arithmetic unit are demonstrated via simulations and experiments. The optical Arithmetic unit can be used
Parallel Saturating Fractional Arithmetic Units
 IN 9TH GREAT LAKES SYMPOSIUM ON VLSI
, 1999
"... This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of ..."
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Cited by 13 (6 self)
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This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output
Results 1  10
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