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120
Proving the Correctness of Pipelined Micro-Architectures
- Proc. of the ITG/GI/GMM Workshop, (Ed K. Waldschmidt and C. Grimm), VDE Verlag
, 2000
"... This paper presents how to generate the implementation of a pipelined microprocessor from an arbitrary sequential specification. All necessary forwarding and stalling logic is created automatically. The implementation is provided in the language of the theorem proving system (PVS). This implementati ..."
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Cited by 4 (1 self)
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This paper presents how to generate the implementation of a pipelined microprocessor from an arbitrary sequential specification. All necessary forwarding and stalling logic is created automatically. The implementation is provided in the language of the theorem proving system (PVS
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
- In Proc. 32nd Annual Intl. Symp. on Microarchitecture
, 1999
"... Building a high-petformance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To&rther complicate this task, deep submicro ..."
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Cited by 374 (15 self)
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of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. Thefunctional checker verifies the correctness of the core processor’s computation, only permitting correct results to commit. Overall design cost can
Formal verification of the ARM6 micro-architecture
, 2002
"... This report describes the formal verification of the arm6 micro-architecture using the hol theorem prover. The correctness of the microprocessor design compares the micro-architecture with an abstract, target instruction set semantics. Data and temporal abstraction maps are used to formally relat ..."
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Cited by 8 (2 self)
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relate the state spaces and to capture the timing behaviour of the processor. The verification is carried out in hol and one-step theorems are used to provide the framework for the proof of correctness. This report also describes the formal specification of the arm6's three stage pipelined micro-architecture.
Correctness of Pipelined Machines
- Formal Methods in Computer-Aided Design–FMCAD 2000, volume 1954 of LNCS
"... The correctness of pipelined machines is a subject that has been studied extensively. Most of the recent work has used variants of the Burch and Dill notion of correctness [4]. As new features are modeled, e.g., interrupts, new notions of correctness are developed. Given the plethora of correctness ..."
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Cited by 32 (13 self)
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]. Briey, our notion of correctness implies that the ISA (Instruction Set Architecture) and MA (Micro-Architecture) machines have the same observable in nite paths, up to stuttering. This implies that the two machines satisfy the same CTL* X properties and the same safety and liveness properties (up
Verifying Micro-Architecture Simulators using Event Traces
"... Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere com ..."
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Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere
Counterflow Pipeline Processor Architecture
, 1994
"... : The counterflow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass. ..."
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Cited by 57 (0 self)
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: The counterflow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass
Proving the Correctness of a Complete Microprocessor
- In GI Jahrestagung 2000
, 2000
"... . This paper presents status results of a microprocessor verification project. The authors verify a complete 32-bit RISC microprocessor including the floating point unit and the control logic of the pipeline. The paper describes a formal definition of a "correct" microprocessor. This co ..."
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Cited by 10 (5 self)
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. This paper presents status results of a microprocessor verification project. The authors verify a complete 32-bit RISC microprocessor including the floating point unit and the control logic of the pipeline. The paper describes a formal definition of a "correct" microprocessor
Using Positive Equality to Prove Liveness for Pipelined Microprocessors
- In Proc. Asia and South Pacific Design Automation Conference
, 2004
"... Abstract—The paper presents an indirect method to automatically prove liveness for pipelined microprocessors. This is done by first proving safety—correctness for one step, starting from an arbitrary initial state that is possibly restricted by invariant constraints. By induction, the implementation ..."
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Cited by 6 (2 self)
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Abstract—The paper presents an indirect method to automatically prove liveness for pipelined microprocessors. This is done by first proving safety—correctness for one step, starting from an arbitrary initial state that is possibly restricted by invariant constraints. By induction
Maurer Computers for Pipelined Instruction Processing
- UNDER CONSIDERATION FOR PUBLICATION IN MATH. STRUCT. IN COMP. SCIENCE
, 2006
"... We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new ..."
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Cited by 11 (8 self)
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We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a
Proving optimizations correct using parameterized program equivalence
- In Proceedings of the 2009 Conference on Programming Language Design and Implementation (PLDI 2009
, 2009
"... Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validation has been used to prove concrete, fully specified programs equivalent. In this paper we present Parameterized Equivale ..."
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Cited by 23 (4 self)
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known property is that it does not modify certain variables. By proving parameterized programs equivalent, PEC can prove the correctness of transformation rules that represent complex optimizations once and for all, before they are ever run. We implemented our PEC technique in a tool that can establish
Results 1 - 10
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120
