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Microprocessor Design Verification

by Warren Hunt, Copyright Warren, A. Hunt - Journal of Automated Reasoning , 1989
"... The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction-level specification ..."
Abstract - Cited by 60 (3 self) - Add to MetaCart
The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32-bit general purpose, von Neumann processor whose design-level (gate-level) specification has been verified with respect to its instruction

Evolutionary test program induction for microprocessor design verification

by Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero - in Proc. 11th IEEE Int. Conf. ATS , 2002
"... Design verification is a crucial step in the design of any electronic device. Particularly when microproces-sor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test pro-gram for maximizing a given verific ..."
Abstract - Cited by 10 (4 self) - Add to MetaCart
Design verification is a crucial step in the design of any electronic device. Particularly when microproces-sor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test pro-gram for maximizing a given

Microprocessor Design Verification by Two-Phase Evolution of Variable Length Tests

by J.E. Smith, M. Bartley, T.C. Fogarty, M. Bartley T. C. Fogarty , 1997
"... This paper discusses the use of a genetic algorithm to generate test programs for the verification of the design of a modern microprocessor. The algorithm directly learns sequences of assembly-code instructions which satisfy a coverage metric for one specific part of a design. The complexity of the ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
This paper discusses the use of a genetic algorithm to generate test programs for the verification of the design of a modern microprocessor. The algorithm directly learns sequences of assembly-code instructions which satisfy a coverage metric for one specific part of a design. The complexity

Automatic Verification of Pipelined Microprocessor Control

by Jerry Burch, David Dill , 1994
"... We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time nee ..."
Abstract - Cited by 290 (7 self) - Add to MetaCart
We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time

Systematic design of program analysis frameworks

by Patrick Cousot, Radhia Cousot - In 6th POPL , 1979
"... Semantic analysis of programs is essential in optimizing compilers and program verification systems. It encompasses data flow analysis, data type determination, generation of approximate invariant ..."
Abstract - Cited by 765 (50 self) - Add to MetaCart
Semantic analysis of programs is essential in optimizing compilers and program verification systems. It encompasses data flow analysis, data type determination, generation of approximate invariant

The model checker SPIN.

by Gerard J Holzmann - IEEE Trans. on Software Eng. , 1997
"... Abstract-SPIN is an efficient verification system for models of distributed software systems. It has been used to detect design errors in applications ranging from high-level descriptions of distributed algorithms to detailed code for controlling telephone exchanges. This paper gives an overview of ..."
Abstract - Cited by 1516 (26 self) - Add to MetaCart
Abstract-SPIN is an efficient verification system for models of distributed software systems. It has been used to detect design errors in applications ranging from high-level descriptions of distributed algorithms to detailed code for controlling telephone exchanges. This paper gives an overview

Bandera: Extracting Finite-state Models from Java Source Code

by James C. Corbett, Matthew B. Dwyer, John Hatcliff, Shawn Laubach, Corina S. Pasareanu, Hongjun Zheng - IN PROCEEDINGS OF THE 22ND INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING , 2000
"... Finite-state verification techniques, such as model checking, have shown promise as a cost-effective means for finding defects in hardware designs. To date, the application of these techniques to software has been hindered by several obstacles. Chief among these is the problem of constructing a fini ..."
Abstract - Cited by 654 (33 self) - Add to MetaCart
Finite-state verification techniques, such as model checking, have shown promise as a cost-effective means for finding defects in hardware designs. To date, the application of these techniques to software has been hindered by several obstacles. Chief among these is the problem of constructing a

Extended Static Checking for Java

by Cormac Flanagan, K. Rustan M. Leino, Mark Lillibridge, Greg Nelson, James B. Saxe, Raymie Stata , 2002
"... Software development and maintenance are costly endeavors. The cost can be reduced if more software defects are detected earlier in the development cycle. This paper introduces the Extended Static Checker for Java (ESC/Java), an experimental compile-time program checker that finds common programming ..."
Abstract - Cited by 638 (24 self) - Add to MetaCart
programming errors. The checker is powered by verification-condition generation and automatic theoremproving techniques. It provides programmers with a simple annotation language with which programmer design decisions can be expressed formally. ESC/Java examines the annotated software and warns

FFTW: An Adaptive Software Architecture For The FFT

by Matteo Frigo, Steven G. Johnson , 1998
"... FFT literature has been mostly concerned with minimizing the number of floating-point operations performed by an algorithm. Unfortunately, on present-day microprocessors this measure is far less important than it used to be, and interactions with the processor pipeline and the memory hierarchy have ..."
Abstract - Cited by 602 (4 self) - Add to MetaCart
FFT literature has been mostly concerned with minimizing the number of floating-point operations performed by an algorithm. Unfortunately, on present-day microprocessors this measure is far less important than it used to be, and interactions with the processor pipeline and the memory hierarchy have

MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems

by Chunho Lee, Miodrag Potkonjak, William H. Mangione-smith
"... Over the last decade, significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of generalpurpose computing, and more specifically the SPEC benchmark suite. At ..."
Abstract - Cited by 966 (22 self) - Add to MetaCart
. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems
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