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226
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
- Formal Methods in System Design
, 1993
"... Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modified form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic "next-time" operator. In its sim ..."
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Cited by 107 (24 self)
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Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modified form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic "next-time" operator. In its
The algorithmic analysis of hybrid systems
- THEORETICAL COMPUTER SCIENCE
, 1995
"... We present a general framework for the formal specification and algorithmic analysis of hybrid systems. A hybrid system consists of a discrete program with an analog environment. We model hybrid systems as nite automata equipped with variables that evolve continuously with time according to dynamica ..."
Abstract
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Cited by 778 (71 self)
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to dynamical laws. For verification purposes, we restrict ourselves to linear hybrid systems, where all variables follow piecewise-linear trajectories. We provide decidability and undecidability results for classes of linear hybrid systems, and we show that standard program-analysis techniques can be adapted
Digital Circuit Verification using Partially-Ordered State Models
- In International Symposium on Multi-Valued Logic
, 1994
"... Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over "weakened" state values. This technique has long been practiced with logic simulators, using the value X to indicate a signal that could be either 0 or 1. This concept can be formally ..."
Abstract
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Cited by 4 (1 self)
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for formal verification that can apply a hybrid of symbolic and partially-ordered evaluation.
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
, 1991
"... Symbolic trajectory evaluation is a new approach to formal hardware verification combining the circuit modeling capabilities of symbolic logic simulation with some of the analytic methods found in temporal logic model checkers. We have created such an evaluator by extending the symbolic switch-level ..."
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Cited by 50 (15 self)
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Symbolic trajectory evaluation is a new approach to formal hardware verification combining the circuit modeling capabilities of symbolic logic simulation with some of the analytic methods found in temporal logic model checkers. We have created such an evaluator by extending the symbolic switch
FORMAL HARDWARE VERIFICATION BY SYMBOLIC TRAJECTORY EVALUATION
, 1997
"... Formal verification uses a set of languages, tools, and techniques to mathematically reason about the correctness of a hardware system. The form of mathematical reasoning is dependent upon the hardware system. This thesis concentrates on hardware systems that have a simple deterministic high-level s ..."
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Cited by 18 (1 self)
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. An implemen-tation mapping is used to relate abstract states to detailed circuit states. The mapping captures the micro-architecture of an implementation of the processor. Symbolic Trajectory Evaluation is used to verify that the circuit fulfills each individual abstract assertion under the implementation
Software Verification with Symbolic Trajectory Evaluation
, 2000
"... Symbolic trajectory evaluation is a model checking approach based on partial order representation of state spaces. It computes the next-state function using symbolic simulation. Symbolic trajectory evaluation has been successful in dealing with large circuits which prompts an examination of the appr ..."
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of propositions about partially ordered state spaces. Using this framework verification conditions called assertions are defined and verified. Symbolic trajectory evaluation still suffers from the state explosion problem. Compositionality is an approach that has been successfully combined with symbolic trajectory
Formal Verification of Content Addressable Memories using Symbolic Trajectory Evaluation
- In DAC’97
, 1997
"... In this paper we report on new techniques for verifying content addressable memories (CAMs), and demonstrate that these techniques work well for large industrial designs. It was shown in [6], that the formal verification technique of symbolic trajectory evaluation (STE) could be used successfully on ..."
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Cited by 22 (3 self)
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In this paper we report on new techniques for verifying content addressable memories (CAMs), and demonstrate that these techniques work well for large industrial designs. It was shown in [6], that the formal verification technique of symbolic trajectory evaluation (STE) could be used successfully
Formal verification of PowerPC arrays using symbolic trajectory evaluation
, 1997
"... assertions IMPLEMENTATION switch-level Figure 4: Tool organization for our verification experiments. ..."
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Cited by 4 (0 self)
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assertions IMPLEMENTATION switch-level Figure 4: Tool organization for our verification experiments.
Coverage Measurement for Software Application Testing using Partially Ordered Domains and Symbolic Trajectory Evaluation Techniques
"... Ensuring the functional correctness of a SoC is essential for successful design projects. A proven and effective method from Freescale Semiconductor Australia is to employ software application testing at the pre-silicon simulation stage. This method was formalized and implemented into a Software App ..."
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from the formal verification domain of Symbolic Trajectory Evaluation. The coverage method was applied to the Nios SoC and experimental coverage results will be discussed. 1.
The Mathematical Foundation of Symbolic Trajectory Evaluation
- In ComputerAided Verification
, 1999
"... . In this paper we elucidate the mathematical foundation underlying both the basic and the extended forms of symbolic trajectory evaluation (STE), with emphasis on the latter. In addition, we make three contributions to the theory of STE which, we believe, are new. First, we provide a satisfactor ..."
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Cited by 21 (0 self)
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used by STE is an abstract interpretation of the ordinary boolean model via a Galois connection. We hope that our exposition will make STE, especially its extended form, less mysterious. 1 Introduction In BDD-based formal verification, symbolic trajectory evaluation (STE) [10, 6] is the main
Results 1 - 10
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226
