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94
Evolutionary test program induction for microprocessor design verification
- in Proc. 11th IEEE Int. Conf. ATS
, 2002
"... Design verification is a crucial step in the design of any electronic device. Particularly when microproces-sor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test pro-gram for maximizing a given verific ..."
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Cited by 10 (4 self)
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Design verification is a crucial step in the design of any electronic device. Particularly when microproces-sor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test pro-gram for maximizing a given
Algebraic models of simultaneous multi-threaded and chip-level multi-threaded microprocessors
- the Journal of Algebraic and Logic Programming
, 2007
"... Abstract. Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state-of-the-art: Simultaneous Multithreaded (SMT) and Multi-core, or Chip-Level Multithreaded (CMT) microprocessor ..."
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Cited by 2 (1 self)
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Abstract. Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state-of-the-art: Simultaneous Multithreaded (SMT) and Multi-core, or Chip-Level Multithreaded (CMT
Task-level Timed-functional Simulation for Multi-core Embedded Systems
"... Abstract—Since the design validation and correction cost is drastically increasing as the design steps proceed, software verification is considerably desired before the simulation model for the target architecture is constructed. As timing correctness is as important as functional correctness in rea ..."
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. Keywords- Task model; multi-processor; timing simulation; functional simulation; multi-task; embedded software I.
EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores
"... Abstract: Core-based system-on-chip (SoC) design is quickly becoming a new paradigm in electronic system design due to the reusability of IP cores. How-ever, the validation of IP cores is the most time consuming task in the design flow. This paper presents EmGen, an automatic test-program generation ..."
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of embedded microprocessor cores. Experiments results show that EmGen can improve verification process and cut down skilled manpower obviously. 1
Core extraction and non-example generation: Debugging and understanding logical models
- Masters thesis, MIT, Computer Science and Artificial Intelligence Laboratory
, 2004
"... Declarative models, in which conjunction and negation are freely used, are a pow-erful tool for software specification and verification. Unfortunately, tool support for developing and debugging such models is limited. The challenges to developing such tools are twofold: technical information must be ..."
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Cited by 3 (0 self)
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be extracted from the model, then that information must be presented to the user in way that is both meaningful and manageable. This document introduces two such techniques to help fill the gap. Non-example generation allows the user to ask for the role of a particular subformula in a model. A formula
SUBMITTED TO IEEE TRANS. M.M. 1 Tri-Subject Kinship Verification: Understanding the Core of A Family
"... Abstract—One major challenge in computer vision is to go beyond the modeling of individual objects and to investigate the bi- (one-versus-one) or tri- (one-versus-two) relationship among multiple visual entities, answering such questions as whether a child in a photo belongs to given parents. The ch ..."
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contributions are three folds: 1) a novel relative symmetric bilinear model (RSBM) introduced to model the similarity between the child and the parents, by incorporating the prior knowledge that a child may resemble a particular parent more than the other; 2) a spatially voted method for feature selection
An Incremental Learning Framework for Estimating Signal Controllability in Unit-Level Verification
"... Abstract—Unit-level verification is a critical step to the success of full-chip functional verification for microprocessor designs. In the unit-level verification, a unit is first embedded in a complex software that emulates the behavior of surrounding units, and then a sequence of stimuli is applie ..."
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that the proposed OBDF algorithm has lower model complexity and lower error variance than the previous algorithms. Meanwhile, a commercial microprocessor core is also applied to demonstrate that controllability of input signals on the load/store unit in the microprocessor core can be estimated automatically
Design Verification for Sequential Systems at Various Abstraction Levels
, 2005
"... With the ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often sur-passes 70 % of the total development cost and the situation has been projected to continue to worsen. The most critical limitations ..."
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for abstraction-refinement based model checking. Experiments on a wide range of industrial designs have shown that the proposed optimizations consistently provide between 1-2 orders of magnitude speedup and can be extremely useful in enhancing the efficacy of existing formal verification algorithms
An Object-Oriented Framework for the Formal Verification of Processors
- In European Conference on Object-Oriented Programming, volume 952 of LNCS
, 1995
"... . We propose an object-oriented approach for the formal verification of processors. This approach has been validated on significant applications. It is based on a class hierarchy that provides the basic components to describe processors at any abstraction level, and to specify verifications to e ..."
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Cited by 1 (1 self)
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to execute. The originality of our method is to combine an object-oriented model (to ensure genericity) and a computer algebra verification system (to ensure efficiency). Computer experiments with our framework clearly shown three main advantages: processor descriptions are very easy to write down
Formal Verification of Components in Java
"... Formal verification of a hierarchical component application involves (i) checking of behavior compliance among sub-components of each composite component, and (ii) checking of implementation of each primitive component against its behavior specification and other properties like absence of concurren ..."
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of concurrency errors. In this thesis, we focus on verification of primitive components implemented in Java against the properties of obeying a behavior specification defined in behavior protocols (frame protocol) and absence of concurrency errors. We use the Java PathFinder model checker as a core verification
Results 1 - 10
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