Abstract— To keep up with the growing complexity of digital systems, high level models are used in the design process. In today’s processor design, a comprehensive tool chain can be built automatically from architectural or transaction level models, but disregarding formal verification. We present

The VIATRA (VIsual Automated model TRAnsformations) framework is the core of a transformation-based verification and validation environment for improving the quality of systems designed using the Unified Modeling Language by automatically checking consistency, completeness, and dependability

In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage

for verifying the implementation of an application program for a customized soft– processor, based on the ACL2 theorem prover. The correctness proof involves verifying a machine code program executing on the target hardware device against a high-level specification of the application program. We illustrate

A few simple Expert-System techniques have been invaluable in developing a new test program generator for design verification of hardware processors. The new generator uses a formal declarative model of the processor architecture; it allows generation of test programs for a variety

As the Model Driven Architecture (MDA) relies on complex and highly automated model transformations between arbitrary modeling languages, the quality of such transformations is of immense importance as it can easily become a bottleneck of a model-driven design process. Automation surely increases

based on Finite State Machines (FSMs). As the area of processor design automation is becoming increasingly inclusive of system paradigms that are heterogeneous in terms of timing, such as multiclock and asynchronous circuits, there is a need for appropriate models and associated synthesis algorithms

In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor’s architectural specification, which may include all aspects

by benchmark applications around the Unified Modeling Language (UML). In the paper, we present a meta-level transformation technique to enable model checking-based symbolic verification for arbitrary well-formed models and modeling languages (with formal semantics defined by graph transformation systems

of supposedly RESTful APIs violate key REST constraints. We show that the constraints of REST and of RESTful HTTP can be precisely formulated within temporal logic. This leads to methods for model checking and run-time verification of RESTful behavior. We formulate several relevant verification questions