This report gives details of a hol specification of the arm instruction set architecture. It is shown that the hol proof tool provides a suitable environment in which to model the architecture. The specification is used to execute fragments of arm code generated by an assembler. The specification

Abstract not found

is designed to be architecture independent whenever possible, making Pintools source compatible across different architectures. However, a Pintool can access architecture-specific details when necessary. Instrumentation with Pin is mostly transparent as the application and Pintool observe the application’s

. This paper presents techniques for specifying microprocessor instruction set syntax and semantics in the HOL theorem proving system. The paper describes the use of abstract representations for operators and data, gives techniques for specifying instruction set syntax, outlines the use

Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instruction sets and variants, and IO configurations. Previous high-performance computing systems have scaled in specific cases

Instruction Set from Yorlaown). DAISY is specifically intended to emulate existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes on the VLIW. Each time a new fragment of code is executed for the first time, the code

Abstract. This paper presents a new HOL4 formalization of the current ARM instruction set architecture, ARMv7. This is a modern RISC architecture with many advanced features. The formalization is detailed and extensive. Considerable tool support has been developed, with the goal of making the model

, cellular phones etc. ARMSim is a lightweight ISA (Instruction Set Architecture) level simulator and a trace generator too. It has some optimizations at the decoder level to improve performance.

The proposed research builds upon previous work at Cambridge on the formal verification of ARM processor hardware and assembly level software. We will use formal models of the ARM4T instruction set architecture (ISA) resulting from the completed EPSRC project Formal Specification and Verification

of the JVM contain a bytecode verifier that statically checks several security constraints before execution of the code. We have formalized large parts of the JVM, covering the central parts of object orientation, within the theorem prover Isabelle/HOL. We have then formalized a specification for a Java