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Table 1. Design parameters
in A hybrid approach for mapping conjugate gradient onto an FPGA-augmented reconfigurable supercomputer
2006
"... In PAGE 5: ...parameters shown in Table1 specify the design character- istics. As shown in Figure 6, the design consists of two pipelined cooperating FPGAs, F1 and F2; and a set of local memory banks to hold the val, col, and jptr vectors.... In PAGE 5: ... There are lg k non-leaf levels in a full binary tree having k leaf nodes. As noted in Table1 , fim and fia are the laten- cies of the floating point IP cores used in this design, so the latency of the dot product core is fim +fia lg k clock cycles. Figure 7(a) shows an example for k = 4.... ..."
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Table 3: Design parameters.
1994
"... In PAGE 4: ... The miss ratios and memory organization are shown in Table 2. To calculate the average access time and miss penalty of each memory level, we assumed a 200 MHz pro- cessor with a disk access time of 5ms { 15ms and a memory system with parameters similar to that in [3] as shown in Table3 . In this design, we observe that m P value for the second level cache range from... ..."
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Table 2. Design Parameters
"... In PAGE 11: ... Figure 8 shows that this increase in link and bank con- tention for the TLCopt designs does not translate into a significant performance degradation compared to the base TLC design. For some benchmarks, the TLCopt designs achieve slight improvements in execution time due to their slightly lower cache access latencies ( Table2 ). Overall multiple partial tag matches in the TLCopt designs occurred in approximately 1% of the cache lookups, thus the increased messages sent between the cache controller and the banks has little effect on performance.... ..."
Table 2. Design Parameters
"... In PAGE 11: ... Figure 8 shows that this increase in link and bank con- tention for the TLCopt designs does not translate into a significant performance degradation compared to the base TLC design. For some benchmarks, the TLCopt designs achieve slight improvements in execution time due to their slightly lower cache access latencies ( Table2 ). Overall multiple partial tag matches in the TLCopt designs occurred in approximately 1% of the cache lookups, thus the increased messages sent between the cache controller and the banks has little effect on performance.... ..."
Table 2 Design parameters
"... In PAGE 8: ... The first example demonstrates the closed orbit mode of operation for pure translational motion. To this aim, it is assumed that the platform parameters are those presented in Table2 and that motors D and F rotate at the same speed and with opposite sense of rotation. According to Eq.... In PAGE 10: ...or that is governed by Eq. H2084911H20850. Most of the parameters of Eq. H2084911H20850 are provided by Table2 . The torque constant may be calculated by the nominal values of Table 1, according to Eqs.... ..."
TABLE 2 DESIGN PARAMETERS
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Table 1: Design Parameters
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Table II Design parameters
TABLE I DESIGN PARAMETERS
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