Results 1 - 10 of 1,553

Tolerating Latency with Dagger

by Attila Gursoy Kale, L. V. Kale
"... The communication latency is a major issue that must be dealt with in parallel computing. The parallel computation model therefore must provide the ability to tolerate such latencies. Communication using blocking receives is the commonly used mechanism in parallel programming today. Message drive ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
The communication latency is a major issue that must be dealt with in parallel computing. The parallel computation model therefore must provide the ability to tolerate such latencies. Communication using blocking receives is the commonly used mechanism in parallel programming today. Message

Tolerating Latency Through Software-Controlled Prefetching in Shared-Memory Multiprocessors

by Todd Mowry, Anoop Gupta - Journal of Parallel and Distributed Computing , 1991
"... The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Although the provision of coherent caches in many recent machines has alleviated the problem somewhat, cache misses still occur frequently enough that they s ..."
Abstract - Cited by 302 (18 self) - Add to MetaCart
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Although the provision of coherent caches in many recent machines has alleviated the problem somewhat, cache misses still occur frequently enough

Tolerating Latency by Prefetching Java Objects

by Brendon Cahoon, Kathryn S. McKinley - In Workshop on Hardware Support for Objects and Microarchitectures for Java , 1999
"... In recent years, processor speed has become increasingly faster than memory speed. One technique for improving memory performance is data prefetching which is successful in array-based codes but only now are researchers applying to pointer-based codes. In this paper, we evaluate a data prefetching t ..."
Abstract - Cited by 10 (1 self) - Add to MetaCart
technique, called greedy prefetching, for tolerating latency in Java programs. In greedy prefetching, when a loop or recursive method updates an object o, we prefetch objects to which o refers. We describe inter- and intraprocedural algorithms for computing objects to prefetch and we present preliminary

Abstract Tolerating Latency by Prefetching Java Objects

by Brendon Cahoon, Kathryn Mckinley
"... In recent years, processor speed has become increasingly faster than memory speed. One technique for improving memory performance is data prefetching which is successful in array-based codes but only now are researchers applying to pointer-based codes. In this paper, we evaluate a data prefetching t ..."
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technique, called greedy prefetching, for tolerating latency in Java programs. In greedy prefetching, when a loop or recursive method updates an object o, we prefetch objects to which o refers. We describe inter- and intraprocedural algorithms for computing objects to prefetch and we present preliminary

ARCHITECTURAL AND COMPILER ISSUES FOR TOLERATING LATENCIES IN HORIZONTAL ARCHITECTURES

by Emre Ozer , 2001
"... This dissertation presents a new architecture model named Weld for horizontal architectures such as VLIW and EPIC. Weld integrates speculative multithreading support into a VLIW/EPIC processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware te ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
This dissertation presents a new architecture model named Weld for horizontal architectures such as VLIW and EPIC. Weld integrates speculative multithreading support into a VLIW/EPIC processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware

ARCHITECTURAL AND COMPILER ISSUES FOR TOLERATING LATENCIES IN HORIZONTAL ARCHITECTURES

by unknown authors , 2001
"... This dissertation presents a new architecture model named Weld for horizontal architectures such as VLIW and EPIC. Weld integrates speculative multithreading support into a VLIW/EPIC processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware te ..."
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This dissertation presents a new architecture model named Weld for horizontal architectures such as VLIW and EPIC. Weld integrates speculative multithreading support into a VLIW/EPIC processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware

TOLERATING LATENCY THROUGH SOFTWARE-CONTROLLED DATA PREFETCHING

by Albert Macovksi , 1994
"... ii ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract not found

A Scalable Content-Addressable Network

by Sylvia Ratnasamy , Paul Francis, Mark Handley, Richard Karp, Scott Shenker - IN PROC. ACM SIGCOMM 2001 , 2001
"... Hash tables – which map “keys ” onto “values” – are an essential building block in modern software systems. We believe a similar functionality would be equally valuable to large distributed systems. In this paper, we introduce the concept of a Content-Addressable Network (CAN) as a distributed infra ..."
Abstract - Cited by 3371 (32 self) - Add to MetaCart
infrastructure that provides hash table-like functionality on Internet-like scales. The CAN is scalable, fault-tolerant and completely self-organizing, and we demonstrate its scalability, robustness and low-latency properties through simulation.

Tolerating latency in replicated state machines through client speculation

by Benjamin Wester, Peter M. Chen, James Cowling, Jason Flinn, Edmund B. Nightingale, Barbara Liskov
"... Replicated state machines are an important and widelystudied methodology for tolerating a wide range of faults. Unfortunately, while replicas should be distributed geographically for maximum fault tolerance, current replicated state machine protocols tend to magnify the effects of high network laten ..."
Abstract - Cited by 14 (0 self) - Add to MetaCart
replies and prioritizing throughput over latency. We then describe a mechanism that allows speculative clients to make new requests through replica-resolved speculation and predicated writes. We implement a detailed case study that applies this approach to a standard Byzantine fault tolerant protocol

Active Messages: a Mechanism for Integrated Communication and Computation

by Thorsten Von Eicken, David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser , 1992
"... The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without sacrificing processor cost/performance. We show that existing message passing multiprocessors have unnecessarily high com ..."
Abstract - Cited by 1054 (75 self) - Add to MetaCart
. With this mechanism, latency tolerance becomes a programming/compiling concern. Hardware support for active messages is desirable and we outline a range of enhancements to mainstream processors.
Results 1 - 10 of 1,553