"... In PAGE 8: ... Rather, the tag is used to steer the access to either a physical register or its register extension based upon the value of the valid bit of the register extension and the MSB of the tag. 6 Evaluation Table3 summarizes the actions taken by the three differ- ent schemes. A common benefit of these schemes is bet- ter register utilization because of reduced register require- ments.... ..."

"... In PAGE 8: ... Rather, the tag is used to steer the access to either a physical register or its register extension based upon the value of the valid bit of the register extension and the MSB of the tag. 6 Evaluation Table3 summarizes the actions taken by the three differ- ent schemes. A common benefit of these schemes is bet- ter register utilization because of reduced register require- ments.... ..."

"... In PAGE 8: ... Rather, the tag is used to steer the access to either a physical register or its register extension based upon the value of the valid bit of the register extension and the MSB of the tag. 6 Evaluation Table3 summarizes the actions taken by the three differ- ent schemes. A common bene t of these schemes is bet- ter register utilization because of reduced register require- ments.... ..."

"... In PAGE 18: ...6 requirements apply to both internal and external interconnections (except that the shielding requirements do not apply for internal). Table2 shows the physical schemes that are compatible with the SSA protocol. Table 2 - SSA physical interconnect schemes Physical Scheme Internal External... ..."

"... In PAGE 17: ...opper version is defined. Future standards may define alternate media and electrical interfaces. The requirements apply to both internal and external interconnections (except that the shielding requirements do not apply for internal). Table1 shows the physical schemes that are compatible with the SSA protocol. Table 1 - SSA physical interconnect schemes Physical Scheme Internal External... ..."

"... In PAGE 5: ... In all cases the proposed scheme had the lowest num ber of bits to be stored. T he reduction of stor age amount with respect to both previously published ap - proaches is summarized in Table2 , which lists the ratios of the storage requirements for the respective schemes. The proposed scheme only requires between 7% and 53 % of the stor age for reseeding of multiple - polynomial LFSRs and between 3 % and 67 % of the storage amount for the method based on twisted ring counters (TRC).... ..."

"... In PAGE 10: ... 5 Analysis and Comparison 5.1 Storage and Communication Costs A comparison of the storage costs is presented in Table1 . Each column represents the tasks discussed in Sections 2.... ..."

"... In PAGE 14: ... Thus, the transfer rate of the RS model is approximately equal to that of the MEMS storage device. Table3 summarizes the difierences between the RS model and the physical MEMS storage model.... ..."

"... In PAGE 6: ... In all cases the proposed scheme had the lowest num ber of bits to be stored. The reduction of stor age amount with respect to both previously published ap - proaches is summarized in Table2 , which lists the ratios ... ..."

"... In PAGE 5: ... However, as these researchers have stated, symbolic methods are hindered by the memory requirement for the storage of the probability vector(s). In Table1 , we summarise the main representative approaches used for over- coming the state space explosion problem when analysing stochastic models. We concentrate on the data structures used to store the matrix and vector, and whether they are stored in- or out-of-core.... In PAGE 6: ... This approach does not have the memory limitations stated for all other implicit methods in Table 1. The first explicit out-of-core method listed in Table1 was introduced by Deavours and Sanders [9,10], where the vector is stored explicitly in RAM as an array and a disk is used to store the matrix explicitly. In [17] this method was further extended by storing the vector as well as the matrix on disk.... ..."