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TABLE 6: MULTI-PROCESSOR SIMULATORS

in Abstract
by Gregory S. Wolffe, Comp Sci Info, William Yurcik

Table 1. Measured levels of grid acceptance and pro- posed systems for MUSICA and GENOMA case stud- ies. MPP stands for Massively Parallel Processor, SMP for Symmetric MultiProcessor and DSM for Dis- tributed Shared-memory Multiprocessor.

in Learning Grid Technologies in a Project-Based Computer Architecture Course
by Guillermo Vega-gorgojo, Yannis A. Dimitriadis, Eduardo Gómez-Sánchez, Miguel L. Bote-lorenzo, Alejandra Martínez-monés
"... In PAGE 6: ... However, we should mention that these results are obtained using the documentation from the rst and second subpro- jects, and therefore are not de nitive and need to be com- pleted after the last subproject is over. The analysis performed shows that most of the students have considered this technology and argued on its suitabil- ity for a real problem, as Table1 illustrates for MUSICA and GENOMA. It was an explicit objective to put the grid in a real context, so this is a major achievement.... ..."

Table 1: Variables in the design space of the heterogeneous multi-processors.

in Design Space Exploration Algorithm For Heterogeneous Multi-processor Embedded System Design
by Ireneusz Karkowski, Henk Corporaal 1998
Cited by 15

Table 3.2: Taxonomy of conventional multi-processor schedulers.

in ShaRE: Run-time System for High-performance Virtualized Routers
by Ravindranath Kokku, Harrick M. Vin, Lorenzo Alvisi, Michael D. Dahlin, Charles G. Plaxton, Ramakrishnan Rajamony, Raj Yavatkar 2005
Cited by 7

Table 3.3: Taxonomy of multi-processor schedulers for comparison.

in ShaRE: Run-time System for High-performance Virtualized Routers
by Ravindranath Kokku, Harrick M. Vin, Lorenzo Alvisi, Michael D. Dahlin, Charles G. Plaxton, Ramakrishnan Rajamony, Raj Yavatkar 2005
Cited by 7

Table 1: Variables in the design space of the heterogeneous multi-processors.

in Exploiting Fine- and Coarse-grain Parallelism in Embedded Programs
by Ireneusz Karkowski And, Ireneusz Karkowski, Henk Corporaal 1998
Cited by 2

TABLE IV RESULTS FOR THE MULTI-PROCESSOR LOAD ASSIGNMENTS.

in Static Task Scheduling Algorithms for Battery Powered DVS Systems
by Princey Chowdhury, Chaitali Chakrabarti

Table 1: Comparison between multi-processors, vector machines, and VLIWs

in —- survey on instruction scheduling
by Yang Yang 2003

Table 3. Data obtained for computing all answer sets with the multi-processor version of platypus.

in Platypus: A platform for distributed answer set solving
by Jean Gressmann, Tomi Janhunen, Robert E. Mercer, Torsten Schaub, Sven Thiele, Richard Tichy 2005
Cited by 5

Table 3: Multi-processor results for speed-metric: 1/3/9/27

in Optimizing Page Replacement for Multiple-Level Memory Hierarchy
by Yi Tian, Edwin H.-M. Sha, Edwin H. -m, Chantana Chantrapornchai, Peter M. Kogge 1998
"... In PAGE 24: ... We assume that each cluster consists of two PIM processors and 4-level memory are available. Table3 presents the results for the system with 1; 3; 9;, and 27 for memory L1 to L4. Table 4 assumes memory accessing time 1; 10; 500, and 20; 000 corresponding to the accessing time for memories L1 to L4.... In PAGE 25: ...LRU method, using Always-Keep, Selectively-Keep, and Selectively-Keep-Sharing respec- tively. From Table3 , take the LU benchmark on 16x16 matrix as an example. Using the modi ed LRU results in the total accessing time 95; 952, while Always-Keep, Selectively- keep and Selectively-Keep-Sharing result in 80; 680, 75; 490, and 54; 322 respectively.... ..."
Cited by 2
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