### Table 11: Importance of optimizing Interconnect at high speed. T is the available time. The area of multiplexers (Mux) is rapidly becoming the dominant part of the overall implementation even when only associated control logic is considered

"... In PAGE 17: ...AT VLSI High Level Synthesis Laws: Theory and Practice 16 of 21 dominate cost of high performance designs. The results from Table11 strongly support this conclusion. For example, we see that in the NEC FIR filter with 126 taps the percentage of the multiplexers as the part of the active area increases from less than 20% when 60 control cycles are available to more than 75% when the available time is reduced to 20 control steps.... ..."

### Tables 1 and 2 describe the sample and indicate that there are significant differences in ROM between the dominant and nondominant side for extension/flexion measures. No significant difference between sides was found for the supination/pronation measures. No associations with ROM were found (all correlation p-values gt; 0.10) for age, years pitched, innings pitched, dominant arm or history of surgery. A logical next step in the analysis would be to develop a multivariate model predicting ROM difference between sides. Since no significant predictor of between- side differences was noted, there is no reason to proceed to a multivariate model.

2005

### Table 13: Concordance, Discordance and Incomparability Levels with S amp;P Ratings

2004

"... In PAGE 20: ... Comparing these results with those presented in Table 8 clearly demonstrates the temporal stability of the logical dominance relationship. Table13 shows the concordance, discordance and incomparability levels between the preference order of S amp;P on one hand, and on the other hand, the logical dominance relationship and the partial orders associated with the logical rating scores and the non-recursive regression scores. Comparing these results with those presented in Table 9 provides additional evidence of the temporal stability of the logical dominance relationship.... ..."

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### Table 4. Industry recipes.

"... In PAGE 11: ... The dominant logic favours a focus on customer PDM, while the competitive logic proposes a focus on PDM in a larger sense. The conflicting features of the industry recipes are presented in Table4 . The different views are mainly due to different understandings of the potential customer segment.... ..."

### Table 4: Critical inputs for binary logic gates and 3-state elements for 5-valued logic

"... In PAGE 6: ...2 Criticality and Test-detect backtrace For step (2) and (5), the critical inputs to binary (logic) gates and 3-state elements have to be defined. To profit from dominant values and the characteristics of specific inputs to elements, they can be defined as shown in Table4 . Only some of the binary gate types are shown since the others can be trivially derived.... In PAGE 7: ...1 Criticality and Test-detect backtrace In order to perform the TD backtraces in parallel, the criticalities for the various element types have to be de- fined in parallel, as shown in Table 5. The expressions are just (vectorized) binary formulations expressing the same as the textual expressions in Table4 in terms of the PP 4-valued signal model, for all inputs and for all possible output values. Obviously, an implementation can be highly optimized; for instance, one would not evaluate the expres- sion for TRINV for its EP or EN input, as these are never critical.... In PAGE 8: ... This is required for an output value 0, and obviously true for an output value 1. In this way, the expression covers both textual expressions for AND in Table4 . Note that the fourth expression checks only the v0 of inputs, since the second factor already excluded Z and U values.... ..."

### Table 2. Synthesis results for primary modules. Logic Elements Memory bits Memory Blocks Feature Engine Datapath and Control 1582 0 0

"... In PAGE 7: ... The Feature Engine throughput is 2 cycles per feature, based on 4 data ports as described earlier. Table2 shows low total use of logic. Logic Element count is based on complex programmable logic blocks found in FPGA chips, and using a rough rule of thumb, the design has 32 to 45 KGates logic (nand2 equivalent) and size is dominated by RAM.... ..."

### Table 1. Performance of multiplication and inversion logic (FPGA Xilinx Virtex II XC2V4000 fi1517-6, F289)

2004

"... In PAGE 7: ... In our design, we have unrolled four loops in MAIA algorithm and we get about two times performance gain in inversion operations with sacriflcing the hardware complexity. The fleld inversion can be performed in an average time of 1:3 s (see Table1 ). The input data that was used to measure the execution time had an Hamming weight of n=2, where n is the bit size of the input data.... In PAGE 8: ... We have implemented LSD flrst digit serial multiplier for this HECC design because it is known that LSD flrst multiplier has better performance than MSD flrst digit serial multi- plier [SP97]. Table1 shows the latency and the area requirement of the digit serial multiplier with various digit sizes. One would expect the frequency of the multipliers to decrease with higher digit size.... In PAGE 8: ... One would expect the frequency of the multipliers to decrease with higher digit size. However, examining Table1 one notices the lower fre- quency for D=1 and D=4 multipliers compared to D=8. Careful analysis shows that the critical path of the D=1 and 4 multipliers are dominated by the control logic, more speciflcally from the comparator logic and addi- tional logic (such as multiplexers).... ..."

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