Results 11 - 20 of 18,214

Table 1: VMMC-2 address translation cost

in VMMC-2: Efficient Support for Reliable, Connection-Oriented Communication
by Cezary Dubnicki, Angelos Bilas, Yuqun Chen, Stefanos Damianakis, Kai Li 1997
Cited by 75

TABLE 1. Classification of Address Translation Mechanisms

in Address Translation Mechanisms in Network Interfaces
by Ioannis Schoinas, Mark D. Hill 1998
Cited by 14

TABLE 1. Classification of Address Translation Mechanisms

in Address Translation Mechanisms in Network Interfaces
by Ioannis Schoinas , Mark D. Hill

TABLE 1. Classification of Address Translation Mechanisms

in Address Translation Mechanisms in Network Interfaces
by Ioannis Schoinas , Mark D. Hill

TABLE 1 Cache Address Translator Tilings

in Cache Tiling for High Performance Morphological Image Processing
by Arun K. Somani, Craig M. Wittenbrink, Craig M. Wittenbrink

Table 3.2: Address translation

in Diplomarbeit — Master’s Thesis Enhancing an ISDN/H.323 Media Gateway Controller to a SIP/H.323 Gateway
by Ausgeführt Zwecke, Erlangung Grades, Fachhochschule Technikum Wien, Studiengang Elektronik, Dipl. -ing Martin Horauer, Fachhochschule Technikum Wien, Dipl. -ing Erik Margraf, Siemens Ag Österreich, Mai Unterschrift

Table 4: Address Translation Time / Total stall

in
by unknown authors

Table 2: Examples of translation errors produced by the SYSTRAN machine translation software.

in The Effect of Pseudo Relevance Feedback on MT-Based CLIR
by Yan Qu, Alla N. Eilerman, Hongming Jin, David A. Evans 2000
"... In PAGE 6: ...7: broken phrase (i.e., a simplex noun phrase is broken up by a preposition or another function word into single word terms, sometimes with an inappropriate part of speech choice). Table2 gives examples of each error type. The second column shows the number of occurrences of a particular error type in the 22 translated French queries.... ..."
Cited by 4

Table 4: Cost of a load for the hit-case in cycles. The Base method corresponds to implementing the handler in C as a runtime library procedure. The three translation mechanisms used are fully mapped, direct mapped and two-way column associative software cache (cost is shown for primary entry). The Inlined version is a hand-optimized inlined handler written in Machsuif. The Hot Pages likely and Hot Pages predictable cases are the handler times for hotpage accesses. The hit-times shown in parenthesis will be achieved in the final version when the start address of the mapped SRAM will be fixed (because we could use a register plus constant offset addressing mode).

in Hot Pages: Software Caching for Raw Microprocessors
by Csaba Andras, Moritz Matthew Frank, Walter Lee, Saman Amarasinghe

Table 4: Cost of a load for the hit-case in cycles. The Base method corresponds to implementing the handler in C as a runtime library procedure. The three translation mechanisms used are fully mapped, direct mapped and two-way column associative software cache (cost is shown for primary entry). The Inlined version is a hand-optimized inlined handler written in Machsuif. The Hot Pages likely and Hot Pages predictable cases are the handler times for hotpage accesses. The hit-times shown in parenthesis will be achieved in the final version when the start address of the mapped SRAM will be fixed (because we could use a register plus constant offset addressing mode).

in Hot Pages: Software Caching for Raw Microprocessors
by Csaba Andras Moritz, Moritz Matthew Frank, Walter Lee, Saman Amarasinghe
Results 11 - 20 of 18,214