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65
Mutation Testing of Software Using a MIMD Computer
, 1992
"... Mutation testing is a fault-based method for testing software that is computationally expensive. Mothra is an interpreter-based mutation testing system that is centered around an interpreter. This paper presents a parallel implementation of Mothra's interpreter on a MIMD machine. The parallel ..."
Abstract
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Cited by 18 (5 self)
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interpreter, HyperMothra, is implemented on a sixteen processor Intel iPSC/2 hypercube. Our goal was to demonstrate that the expense of software testing schemes such as mutation can be reduced by using parallel processing, and we demonstrate this by measuring the performance gains of the parallel interpreter
Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
"... Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext functionality ..."
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Cited by 1 (1 self)
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Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext
SuperMatrix for the Factorization of Band Matrices FLAME Working Note #27
, 2007
"... We pursue the scalable parallel implementation of the factorization of band matrices with medium to large bandwidth targeting SMP and multi-core architectures. Our approach decomposes the computation into a large number of fine-grained operations exposing a higher degree of parallelism. The SuperMat ..."
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Matrix run-time system allows an out-of-order scheduling of operations and a blocked packed storage for band matrices that are transparent to the programmer. Experimental results for the Cholesky factorization of band matrices on a CC-NUMA platform with sixteen processors demonstrate the scalability
Heat Spreading Aware Floorplan for Chip Multicore Processor1
"... Abstract. With more cores integrated into one chip and multiple threads running concurrently on the chip, power consumption from the running threads increases dramatically, and then causes the thermal of the chip going much higher than before. Existed schemes to leverage the thermal problem for a ch ..."
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Cited by 1 (0 self)
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up with a floorplan for a multicore processor which leaves the potential hotspots in different cores as far away from each other as possible. As an example, we show heat spreading aware floorplans for a four cores ' processor and a sixteen cores ' processor respectively. Coupling
Massively Parallel Systolic Processors For High-Speed Recognition Of Simple Patterns
"... This paper describes two systolic array processors, which have been designed for high-speed pattern recognition. Both operate on pixel images and execute the recognition process within 5 µs to 20 µs. The patterns which are recognized are simple geometrical figures, namely ill-defined circles and lin ..."
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Cited by 1 (1 self)
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transform is composed of sixteen X3090 chips (Xilinx). The Euler processor has been mapped into a ...
A NOVEL SLOTTED-RING ARCHITECTURE FOR PARALLEL PROCESSING: AN APPLICATION
"... A novel efficient bus architecture is presented together with an application. The bus architecture belongs to a slotted-ring class. 32-bits of data, 14ibits address, and signalling buses span across a maximum of sixteen proces-sors configured in a ring.?he bus infmnation arriving at each processing ..."
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A novel efficient bus architecture is presented together with an application. The bus architecture belongs to a slotted-ring class. 32-bits of data, 14ibits address, and signalling buses span across a maximum of sixteen proces-sors configured in a ring.?he bus infmnation arriving at each processing
False Sharing and its Effect on Shared Memory Performance
- IN PROCEEDINGS OF THE USENIX SYMPOSIUM ON EXPERIENCES WITH DISTRIBUTED AND MULTIPROCESSOR SYSTEMS (SEDMS IV
, 1993
"... False sharing occurs when processors in a shared-memory parallel system make references to different data objects within the same coherence block (cache line or page), thereby inducing "unnecessary" coherence operations. False sharing is widely believed to be a serious problem for parallel ..."
Abstract
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Cited by 69 (4 self)
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False sharing occurs when processors in a shared-memory parallel system make references to different data objects within the same coherence block (cache line or page), thereby inducing "unnecessary" coherence operations. False sharing is widely believed to be a serious problem
C.1.1 Computer Systems Organization: PROCESSOR ARCHITECTURES Single Data Stream Architectures Von
"... In our computer architecture course, we ask students to design an instruction set for an eight- or sixteen-bit computer and then implement that design in an emulated computer using a logic emulation package. In Winter semester 2006 a team of three students decided to design and implement the “Marie ..."
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In our computer architecture course, we ask students to design an instruction set for an eight- or sixteen-bit computer and then implement that design in an emulated computer using a logic emulation package. In Winter semester 2006 a team of three students decided to design and implement the “Marie
Process Migration Effects on Memory Performance of Multiprocessor Web-Servers
"... Abstract. In this work we put into evidence how the memory performance of a Web-Server machine may depend on the sharing induced by process migration. We considered a shared-bus shared-memory multiprocessor as the simplest multiprocessor architecture to be used for accelerating Web-based and commerc ..."
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four-processor and a high-performance sixteen-processor machine. We show that, even in the four-processor case, the overhead induced by the sharing of private data as a consequence of process migration, namely passive sharing, cannot be neglected. Then, we consider the sixteen-processor case, where
Second-order Recursive Oscillators for Musical Additive Synthesis Applications on SIMD and VLIW Processors
- SIMD and VLIW processors,” in Proc. Int. Computer Music Conf. (ICMC
, 1999
"... This paper summarizes our work adapting a recursive digital resonator for use on sixteen-bit fixed-point hardware. The modified oscillator is a two-pole filter with error properties expressly matched to use in the range of frequencies relevant to additive synthesis of digital audio. We present the a ..."
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Cited by 4 (1 self)
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This paper summarizes our work adapting a recursive digital resonator for use on sixteen-bit fixed-point hardware. The modified oscillator is a two-pole filter with error properties expressly matched to use in the range of frequencies relevant to additive synthesis of digital audio. We present
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