Tools
Sorted by:
Try your query at:
 |
 |
 |
 |
 |
 |
Results 11 - 20
of
6,622
The New Routing Algorithm for the ARPANET
- IEEE TRANSACTIONS ON COMMUNICATIONS
, 1980
"... The new ARPANET routing algorithm is an improvement test results. This paper is a summary of our conclusions only; over the old procedure in that it uses fewer network resources, operates on for more complete descriptions of our research findings, see more realistic estimates of network conditions, ..."
Abstract
-
Cited by 300 (2 self)
- Add to MetaCart
overhead and CPU overhead are 60th less than two percent, most nodes learn of an update within 100 ms, and the algorithm detects congestion and routes packets around congested areas.
Larrabee: a many-core x86 architecture for visual computing
- In SIGGRAPH ’08: ACM SIGGRAPH 2008 papers
, 2008
"... Abstract 123 This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector proces ..."
Abstract
-
Cited by 279 (12 self)
- Add to MetaCart
Abstract 123 This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector
A Network on Chip Architecture and Design Methodology
- In IEEE Computer Society Annual Symposium on VLSI
, 2002
"... We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches and resou ..."
Abstract
-
Cited by 212 (21 self)
- Add to MetaCart
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches
Scratchpad Memory: A Design Alternative for Cache On-chip memory in Embedded Systems
- In Tenth International Symposium on Hardware/Software Codesign (CODES), Estes Park
, 2002
"... In this paper we address the problem of on-chip memory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using t ..."
Abstract
-
Cited by 200 (16 self)
- Add to MetaCart
In this paper we address the problem of on-chip memory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using
On the yield of VLSI processors with on-chip CPU cache, Trans
- on Computers
, 1999
"... Abstract—Yield enhancement through the acceptance of partially good chips is a well-known technique [1], [2], [3]. In this paper, we derive a yield model for single-chip VLSI processors with partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip ..."
Abstract
-
Cited by 3 (0 self)
- Add to MetaCart
CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area, and various manufacturing process parameters as defect densities and the fault clustering parameter. One of the main conclusions is that the maximum effective
Applying Time Warp to CPU Design
- In High Performance Computing Conference '97
, 1997
"... This paper exemplifies the similarities in Time Warp and computer architecture concepts and terminology, and the continued trend for convergence of ideas in these two areas. Time Warp can provide a means to describe the complex mechanisms being used to allow the instruction execution window to be en ..."
Abstract
-
Cited by 6 (5 self)
- Add to MetaCart
This paper exemplifies the similarities in Time Warp and computer architecture concepts and terminology, and the continued trend for convergence of ideas in these two areas. Time Warp can provide a means to describe the complex mechanisms being used to allow the instruction execution window
Applying Time Warp to CPU Design
- In High Performance Computing Conference '97
, 1997
"... This paper exemplifies the similarities in Time Warp and computer architecture concepts and terminology, and the continued trend for convergence of ideas in these two areas. Time Warp can provide a means to describe the complex mechanisms being used to allow the instruction execution window to be en ..."
Abstract
- Add to MetaCart
This paper exemplifies the similarities in Time Warp and computer architecture concepts and terminology, and the continued trend for convergence of ideas in these two areas. Time Warp can provide a means to describe the complex mechanisms being used to allow the instruction execution window
Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures
- In Proceedings of the 42nd Annual Symposium on Microarchitecture
, 2009
"... This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamen ..."
Abstract
-
Cited by 192 (4 self)
- Add to MetaCart
for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic
Perspectives: Complex Adaptations and the Evolution of Evolvability
, 1996
"... The problem of complex adaptations is studied in two largely disconnected research traditions: evolutionary biology and evolutionary computer science. This paper summarizes the results from both areas and compares their implications. In evolutionary computer science it was found that the Darwinian p ..."
Abstract
-
Cited by 223 (8 self)
- Add to MetaCart
The problem of complex adaptations is studied in two largely disconnected research traditions: evolutionary biology and evolutionary computer science. This paper summarizes the results from both areas and compares their implications. In evolutionary computer science it was found that the Darwinian
The filter cache: An energy efficient memory structure
- In Proceedings of the 1997 International Symposium on Microarchitecture
, 1997
"... Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many ..."
Abstract
-
Cited by 222 (4 self)
- Add to MetaCart
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many
Results 11 - 20
of
6,622
