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Table 3. Comparison of the accelerated systems.

in Fast Search for Large Vocabulary Speech Recognition
by Stephan Kanthak, Achim Sixtus, Sirko Molau, Ralf Schlüter, Hermann Ney 2000
"... In PAGE 14: ...described in Section 2. Results are shown in Table3 . For each best performing system shown in Table 2, there is an accelerated version in Table 3.... In PAGE 14: ... Results are shown in Table 3. For each best performing system shown in Table 2, there is an accelerated version in Table3 . The acceleration parameters are chosen in such a way that the word error rate goes up by 0.... In PAGE 14: ... The XW-light system, however, is only 20 % slower than the WW system. As can be seen in Table3 , VTN allows for more efficient pruning. Thus, the combined WW + VTN system is fastest and was chosen for integration into the VERBMOBIL prototype system.... ..."
Cited by 6

Table. 1 @ Parameters of RF acceleration system

in A Ferrite Loaded Untuned Cavity for a Compact Proton Synchrotron
by Hirota Hiramoto Nishi, K. Hiramoto, M. Nishi, Y. Iwashita, A. Noda, M. Inoue

Table D.1: implementation metrics for accelerator system

in Computer Engineering
by Msc Thesis

Table 4: Comparison of the accelerated systems. search space word errors [%]

in Within-Word vs. Across-Word Decoding for Online Speech Recognition
by Stephan Kanthak, Achim Sixtus, Sirko Molau, Hermann Ney, Lehrstuhl Fur Informatik Vi 2000
"... In PAGE 6: ...5% absolute. Results are shown in Table4 . For each best performing system shown in Table 3, there is an accelerated version in Table 4.... In PAGE 6: ...ate goes up by at most 0.5% absolute. Results are shown in Table 4. For each best performing system shown in Table 3, there is an accelerated version in Table4 . The RTF of the WW system decreases by a factor of 5.... ..."
Cited by 1

Table 5: Comparison of accelerated speech recognition systems

in Efficient Vocal Tract Normalization in Automatic Speech Recognition
by Sirko Molau, Stephan Kanthak, Hermann Ney 2000
"... In PAGE 6: ...1%). Thus, also in recognition systems that are accelerated to near real-time ( Table5 ) we observe a signi cantly improved WER of 24.8% from VTN compared to 26.... ..."
Cited by 2

Table 13.1: Schedule of the KEKB accelerator control system development.

in Chapter 13 Accelerator Control System
by System Requirements

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier Jonathan, Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal 1994
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."
Cited by 27

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier, Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal 1994
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."
Cited by 27

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier , Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."

Table 4: SW run times on idle system and using accelerator attached by original and FastLane memory subsystem implementations

in Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms
by Holger Lange, Andreas Koch
"... In PAGE 9: ...3. The set of measurements shown in Table4 quantifies the influence of the different mem- ory attachments on the execution time of software running on the processor that also access main memory in different load patterns. The results show that, despite its high throughput to the HW accelerator, FastLane does not significantly impair the processor: SW execution times are almost unaffected by the HW memory transfer, owing to the absolute priority of the CPU (cf.... ..."
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