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Abstract: . This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a tablebased representation called a MAETT. We express invariant properties of pipelined implementations by specifying relations between fields in the MAETT. To show the viability of this technique, we have proved the correctness ... (Update)
Context of citations to this paper: More
...been developed in the past. Theorem proving techniques, for example, have been successfully adapted to verify pipelined processors ( 3] [16], 18] However, these approaches require a great deal of user in tervention, especially for verifying control intensive designs. Burch...
...been developed in the past. Theorem proving techniques, for example, have been successfully adapted to verify pipelined processors ( 5] [13] [15] Burch and Dill presented a technique for formally verifying pipelined processor control circuitry [4] The technique has been...
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11: Techniques for verifying superscalar microprocessors (context) - Burch - 1996
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BibTeX entry: (Update)
J. Sawada, and W. A. Hunt, Jr., "Trace Table Based Approach for Pipelined Microprocessor Verification, " CAV `97, O. Grumberg, ed., LNCS 1254, Springer-Verlag, June 1997, pp. 364-375. http://citeseer.ist.psu.edu/sawada97trace.html More
@inproceedings{ sawada97trace,
author = "J. Sawada and W. A. Hunt",
title = "Trace Table Based Approach for Pipelined Microprocessor Verification",
booktitle = "Proc. 9th International Computer Aided Verification Conference",
pages = "364--375",
year = "1997",
url = "citeseer.ist.psu.edu/sawada97trace.html" }
Citations (may not include all citations):1575 Computer Architecture a Quantitative Approach (context) - Hennessey, Patterson - 1996
334 A Computational Logic Handbook (context) - Boyer, Moore - 1988
48 Techniques for verifying superscalar microprocessors (context) - Burch - 1996
47 Formal Verification of a Pipelined Microprocessor (context) - Srivas, Bickford - 1990
33 A Formal HDL and Its Use in the FM9001 Verification - Hunt, Brock - 1992
33 ACL2: An Industrial Strength Version of Nqthm - Kaufmann, Moore - 1996
33 Microprocessor verification in PVS: A methodology and simple.. - Cyrluk - 1993
28 Efficient Validity Checking for Processor Verification - Jones, Dill et al. - 1995
24 A Correctness Model for Pipelined Microprocessors - Windley, Coe - 1995
14 Reasoning About Pipelines with Structural Hazards (context) - Agaard, Leeser - 1995
11 Formal Verification of a Commercial Microprocessor (context) - Srivas, Miller - 1995
7 Formal Verification of Pipeline Conflicts in RISC Processors - Tahar, Kumar - 1994
6 Dill: Automatic Verification of Pipelined Microprocessor Con.. (context) - Burch - 1994
4 Burch: Mechanically Checking a Lemma Used in an Automatic Ve.. (context) - Windley - 1996
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Documents on the same site (http://www.cs.utexas.edu/users/sawada/):
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