Repeater block planning under simultaneous delay and transition time constraints (2001) [4 citations — 1 self]

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by Probir Sarkar, Cheng-kok Koh

In Design, Automation and Test in Euro. Conf

http://dynamo.ecn.purdue.edu/~chengkok/papers/date01_repeater.ps

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@INPROCEEDINGS{Sarkar01repeaterblock,
    author = {Probir Sarkar and Cheng-kok Koh},
    title = {Repeater block planning under simultaneous delay and transition time constraints},
    booktitle = {In Design, Automation and Test in Euro. Conf},
    year = {2001},
    pages = {540--544}
}

Abstract:

We present a solution to the problem of repeater block planning under both delay and signal transition time constraints for a given floorplan. Previous approaches have considered only meeting the target delay of a net. However, it has been observed that the repeater planning for meeting the delay target can cause signals on long interconnects to have very slow transition rates. Experimental results show that our new approach satisfies both timing constraints for an average of 79 % of all global nets for six MCNC benchmark floorplans studied (at 1GHz frequency), compared with an average of 22 % for the repeater block planner in [11]. 1.

Citations

333	Interconnections and Packaging for VLSI – Bakoglu, Circuits - 1990
303	The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers – Elmore - 1948
94	Performance optimization of VLSI interconnect layout – Cong, He, et al. - 1996
94	Optimal wire sizing and buffer insertion for low power and a generalized delay model – Lillis, Lin - 1996
58	Wire segmenting for improved buffer insertion – Alpert, Devgan - 1997
56	Buffer placement in distributed RC-tree networks for minimal Elmore delay – Ginneken - 1990
55	Buffer block planning for interconnect-driven floorplanning – Cong, Kong, et al. - 1999
45	Buffer insertion for noise and delay optimization – Alpert, Devgna, et al. - 1999
21	Routability-driven repeater block planning for interconnect-centric floorplanning – Sarkar, Sundararaman, et al. - 2000
10	Partitioning by iterative deletion – Madden - 1999
1	Noise-aware repeater insertionand wire-sizing for on-chip interconnect using hierarchical moment-matching – Chen, Menezes - 1999

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