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Abstract: Dealing effectively with memory access latency is one of the key challenges in the design of shared-memory multiprocessors. Processor caches offer a way to reduce this latency but also give rise to the problem of cache coherence. Existing software solutions to the cache coherence problem are usually inefficient, while hardware solutions are typically complex and expensive to implement. In this thesis, we present a new class of software cache coherence strategies based upon the integration of a... (Update)
Context of citations to this paper: More
.... model of shared memory through a combination of an access control programming model and various software cache coherence protocols [SGZ93, San95]. The key performance benefit of the SR approach is to always allow the caching of shared data. Programs written for the relaxed...
...be able to insert these annotations into the program automatically once the set of shared regions have been identified by the user. In [24], we also consider another alternative for avoiding the programming overhead of SR, using architecture level mechanisms that automatically...
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BibTeX entry: (Update)
H.S. Sandhu. Shared Regions: A Strategy for Efficient Cache Management in Shared-Memory Multiprocessors. Ph.D. Thesis, University of Toronto, July 1995. http://citeseer.ist.psu.edu/sandhu95shared.html More
@phdthesis{ sandhu95shared,
author = "H. S. Sandhu",
title = "Shared Regions: {A} Strategy for Efficient Cache Management in Share-Memory Multiprocessors",
year = "1995",
url = "citeseer.ist.psu.edu/sandhu95shared.html" }
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